Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output command process
Reexamination Certificate
1998-07-16
2001-03-20
Lee, Thomas C. (Department: 2782)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output command process
C710S028000, C710S036000, C710S052000, C365S189020, C370S390000, C711S005000
Reexamination Certificate
active
06205493
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of data communications. More specifically, it relates to the field of serial port access to registers and to the field of serial port access to multiple registers.
2. The Prior Art
Numerous applications take advantage of register-based serial ports. A device may contain a plurality of registers which communicate with a serial port from which data is written into the registers and to which data is read from the registers. A system may include a plurality of such devices each having its own plurality of registers.
An example of a system in the prior art to which the present invention is relevant is the IEEE Standard 802.3u, clause 22. IEEE standard 802.3u defines the logical, electrical, and mechanical characteristics for the Reconciliation sublayer and Media Independent Interface (MII) between CSMA/CD media access controllers and various physical layer devices.
The physical layer devices in this system may have a management port which is a register-based serial port. During system operation, data may be written to and read from individual ones of the registers in the physical devices.
Communication in such a system is packet based. A packet of information asserted on the serial port contains a read/write operation identifier, an address of the physical device containing the register of interest, an address of the register of interest within that device, and, if the operation is a write operation, the data to be written into the register. As will be appreciated by those of ordinary skill in the art, the packet also contains bits used to synchronize the receipt of the information contained therein.
While these systems have performed satisfactorily in the prior art, they are inefficient when read or write operations to multiple registers are to be performed. In order to read or write from or to multiple registers in the same physical device, individual packets must be asserted on the bus to which the serial port is connected. This necessarily consumes valuable bandwidth.
OBJECTS AND ADVANTAGES OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method for accessing multiple registers over a serial port in a register-based serial port device in a single operation.
It is a still further object of this invention to provide a multiple-register-access-capable register-based serial port device.
These and many other objects and advantages of the present invention will become apparent to those of ordinary skill in the art from a consideration of the drawings and ensuing description of the invention.
SUMMARY OF THE INVENTION
In accordance with the present invention, apparatus and methods for multiple register access of a register-based serial port device are disclosed.
A multiple-register-access-capable device according to the present invention includes a plurality of registers and a serial port with which the plurality of registers communicate. Communications packets arriving on the serial port include information identifying the device and register within the device for which they are destined. Packets either contain data to be written into the destination register,or contain data that are to be written out to the serial port.
Since not all hardware and software will support multiple register access, the multiple-register-access-capable device of the present invention is equipped with the capability to turn the multiple register access mode on and off. This allows the multiple-register-access-capable device of the present invention to be used in systems which do not support multiple register access. The multiple register access mode is turned on before multiple register access is attempted.
The multiple-register-access-capable device of the present invention includes a serial port coupled to a plurality of registers. The multiple-register-access-capable device of the present invention is controlled by a state machine or some equivalent logic block. Information written into the multiple-register-access-capable device of the present invention (usually a single bit in one of the registers, a pin on the integrated circuit, etc.) identifies whether the multiple-register-access-capable device of the present invention is in a single-register or multiple-register mode. The state machine which controls the device operates in a single-register mode if the bit is disabled and operates in a multiple-register mode if the bit is enabled.
In single-register mode, the multiple-register-access-capable device of the present invention operates in a manner known in the prior art whereby a single register is identified for reading or writing and data are then either written into the register or read out from the register in response to a write or read request. In multiple register mode, data are written into or read out from all registers or from a group of registers in the device in response to the write or read request.
When the multiple-register-access-capable device of the present invention is in multiple-register access mode, a read or write operation addressed to a selected register is interpreted as a request to read or write from all registers in a defined group of registers and the state machine directs the operation of the device to accomplish a read from or write to all of the registers in the group. When the multiple-register-access-capable device of the present invention is in single-register mode, operations addressed to the selected register cause normal read or write operation to be executed with respect to that register.
According to a method of the present invention, a multiple-register-access-capable device of the present invention may be in single-register access mode or in multiple-register access mode. In single-register access mode, the device is compatible with prior-art devices and operates in the manner known in the prior art for single-register read and write operations. According to a presently preferred embodiment of the present invention, placing the multiple-register-access-capable device of the present invention into single-register or multiple-register mode may be accomplished by setting or resetting a multiple-register-access bit which occupies a selected bit position in one of the registers in the device.
When in single-register access mode, the state machine controlling the operation of the device is caused to operate the device in the manner well known in the prior art. When in multiple-register access mode, the state machine controlling the operation of the device is caused to operate the device in the manner well known in the prior art unless a selected register is addressed for a read or write operation. When the selected register is addressed, the state machine causes the device to perform the requested read or write operation on a plurality of registers, usually all of the registers in the device.
Thus, in multiple-register mode, a write frame asserted at the serial port of the device addressed to the selected register will have a data field comprising all of the data to be written into all of the plurality of registers. Likewise, a read frame asserted at the serial port of the device addressed to the selected register will cause all of the plurality of registers to drive their contents onto the serial port.
In a communications system according to the present invention, one or more driving devices are connected to a serial bus. One or more multiple-register-access-capable devices disclosed herein are also connected to the serial bus.
REFERENCES:
patent: 4760572 (1988-07-01), Tomikawa
patent: 4984251 (1991-01-01), Perloff et al.
patent: 5079766 (1992-01-01), Richard et al.
patent: 5113507 (1992-05-01), Jaeckel
patent: 5179554 (1993-01-01), Lomicka et al.
patent: 5249183 (1993-09-01), Wong et al.
patent: 5251203 (1993-10-01), Thompson
patent: 5287503 (1994-02-01), Narad
patent: 5530888 (1996-06-01), Amasaki et al.
patent: 5542067 (1996-07-01), Chappell et al.
patent: 5659784 (1997-08-01), Inaba et al.
Dreyer Stephen F.
Hu Rong-Hui
Lee Thomas C.
LSI Logic Corporation
Nguyen Tanh
LandOfFree
State machine for selectively performing an operation on a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with State machine for selectively performing an operation on a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and State machine for selectively performing an operation on a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2466728