State machine design for generating half-full and half-empty fla

Details State machine design for generating half-full and half-empty fla State machine design for generating half-full and half-empty fla

1998-08-31

1999-11-23

Chan, Eddie P.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

711156, G06F 1200

Patent

active

059918349

ABSTRACT:
A state machine design which can be used to realize extremely short flag generation delays. The present invention also realizes the benefit of having an extremely high MTBF. The present invention generates a set of next state variables that are generated from a combination of three previous state variables and three additional inputs representing a logical "OR" of a read half-full and write half-full flag WRH, an external write clock input, and an external read clock input. The next state variables are derived from a product of the previous state variables, a complement signal of the previous state variables, and the signal WRH. The half-full flag is generated using digital logic decoding techniques that manipulate inputs from the three next state variables, a read clock signal and a write clock signal.

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