Latency control circuit and method using queuing design method
Latency dependent data bus transmission
Latency insensitive FIFO signaling protocol
Launch raw packet on remote interrupt
Layered crossbar for interconnection of multiple processors...
Layered crossbar for interconnection of multiple processors...
Lazy handling of end of interrupt messages in a virtualized...
Lempel Ziv compression architecture
Limiting write data fracturing in PCI bus systems
Line concentrator with storage function
Line terminating device
Linearly expandable self-routing crossbar switch
Lingering locks with fairness control for multi-node...
Link bus between control chipsets and arbitration method...
Link bus for a hub based computer architecture
Link extender having equalization circuitry
Link extender having equalization circuitry
Link layer controller that provides a memory status signal...
Link layer device with configurable address pin allocation
Link/transaction layer controller with integral...