Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2007-01-02
2007-01-02
Myers, Paul R. (Department: 2112)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C370S229000, C370S394000, C370S449000, C370S466000, C370S516000, C370S395420, C710S003000, C710S033000, C710S100000, C709S232000, C341S102000
Reexamination Certificate
active
10744567
ABSTRACT:
Techniques are disclosed for flexible allocation of address pins of an interface bus to particular sub-buses of the interface bus. The interface bus is between at least one physical layer device and a link layer device in a communication system. Each of the sub-buses has an interface block of the link layer device associated therewith, the interface bus being configurable to carry a composite address signal having a plurality of portions each associated with one of the address pins of the interface bus. The interface blocks of the link layer device are controlled such that each of at least a subset of the interface blocks utilizes only particular ones of the address pins that are controllably allocated to the associated sub-bus in accordance with configuration information stored in the link layer device. The composite address signal is generated as a combination of address outputs of the interface blocks.
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Khan Asif Q.
Kramer David B.
Agere Systems Inc.
Misiura Brian
Myers Paul R.
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