Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-10-13
2003-01-28
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S052000, C703S023000, C370S438000
Reexamination Certificate
active
06513085
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention pertains in general to receiving data from a serial bus of the IEEE 1394 type and, more particularly, to interfacing that data to a peripheral unit in a host system without the requirement for a separate microcontroller.
BACKGROUND OF THE INVENTION
The IEEE has approved a new standard under IEEE 1394 for a high-performance serial bus cable environment that includes a network of logical nodes connected by point-to-point links called physical connections. The physical connections consist of a port on each of the nodes and a cable disposed therebetween. A node can have multiple ports, which allows a branching multi-hop interconnect. The limitations on this topology are set by the requirement for the fixed round-trip time required for the arbitration protocol. The default timing set after a bus reset is adequate for 16 cable hops, each of 4.5 meters for a total of 72 meters. The maximum number of nodes supported on a single bus is 63.
Whenever a node is added to or removed from the 1394 serial bus, a bus reset occurs and forces all nodes to a known state. After a bus reset, the tree identify (ID) process translates the general network topology into a tree, where one node is designated a root, and all the physical connections are labeled as either a parent, a child or as unconnected. The unconnected ports are labeled as “off” and do not participate any further. The tree must be acyclic, meaning no loops allowed; otherwise, the tree ID process will not be completed.
The 1394 cable environment supports multiple data rates of 98.304, 196.608, 393.216 megabits per second. The lowest speed is known as the base rate, and all ports that support a higher data rate must also support the lower data rate. Nodes capable of data rates greater than the base rate exchange speed information with its peers through its attach ports during the speed signaling phase of normal bus arbitration. If a peer node is incapable of receiving high-speed data, then data will not propagate down that path. Data will only be propagated down paths that support the higher data rate.
During data packet transmission, the source node sends a speed code, format and transaction codes, addresses of the source and destination nodes and data in a packet form. The destination field in this packet is utilized by each node's link layer to determine if it is the recipient of the transmitted data. The maximum speed at which a data packet can be transmitted depends upon the bus topology and the data transmission speed supported by the nodes on the bus. To determine the optimum speed at which a data packet may be sent, the maximum supported speeds of the transmitting and receiving nodes, as well as the maximum speeds of any nodes connected between these nodes, must be determined. The optimum speed for data transmission is equal to the highest speed which is supported by all the nodes, which are required to participate in the transmission of the data packet.
The IEEE 1394 bus typically requires a physical layer for extracting information from the bus at a transaction/link layer for interfacing the extracted data from the bus to a host system. The host system typically comprises a host bus and a CPU. The CPU is generally given the task of extracting information from a FIFO in which data from the bus is stored. This data, after being fetched by the CPU, is then transmitted to the appropriate peripheral unit or utilized in various processing operations by the CPU. The CPU can also send information to the serial bus by first storing it in the FIFO and then providing instructions to the link/transaction layer to retrieve the information from the FIFO and transmit it to the serial bus. However, due to the fact that a separate CPU or microcontroller is required, this makes the IEEE1394 bus less attractive for small applications such as digital microphones, stereo receivers and transmitters, etc.
SUMMARY OF THE INVENTION
The present invention disclosed and claimed herein comprises a serial bus interface disposed on a local node for interfacing between a serial bus and a host system and for receiving information from the serial bus placed thereon by a remote node, and transferring this received data to the host system, and receiving information from the host system and transferring the received information to the serial bus for reception by the remote node. The interface includes a data receiver for receiving data generated by the remote node from the serial bus, and a data transmitter for transmitting data to the serial bus for receipt at the remote node. A plurality of registers are also provided, at least one of the registers addressable by the remote node for storage of received data therein. The data receiver is operable to store received data in at least one register during a read operation with a transmitter operable to transmit data to the serial bus during a Write operation. A host bus interface is provided to interface directly with a host bus on the host system, the host bus interface operable to transfer data stored in the at least one register to the host bus during a Write operation when the data is received and stored in the at least one register. It is also operable to retrieve data from the host bus during a Read operation.
In another aspect of the present invention the interface includes a standard register space, wherein at least one register occupies a portion of the standard register space. Select ones of the plurality of registers are dedicated to storage of standard bus information and the remote node can directly access this information. The data receiver is operable to recognize a request for access to one of the plurality of registers and the data transmitters are then operable to transmit the contents thereof when addressed. Select ones of the plurality of registers contain configuration registers for storing configuration information therein that define the operation of the serial bus interface. This allows the remote node to program the operation of the serial bus interface by accessing one of the configuration registers.
In a further aspect of the present invention, data is received in data packets and transmitted in data packets. These data packets comprise information necessary to identify the transmitting node on the serial bus and the content of the data packet in addition to information identifying the remote node designated to receive the packet. Each data reception or data transmission operation is proceeded by a data request, a Write request or Read request, respectively, from the remote node, which requests are contained in the received data packet. The received data packet associated with a Write request contains the data associated therewith, which data is stored in at least one register upon receipt thereof. The host interface recognizes Write requests and then transfers the data stored the at least one register to the host bus. During a Read request, the host interface recognizes the Read request and access the data from the host for transfer to remote node with data transfer.
REFERENCES:
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patent: 6138196 (2000-10-01), Takayama et al.
patent: 6157972 (2000-12-01), Newman et al.
patent: 6272499 (2001-08-01), Wooten
patent: 6327637 (2001-12-01), Chang
patent: 6347097 (2002-02-01), Deng
Gugel Robert G.
Henehan Burke S.
Newman Merril R.
Brady III Wade James
Ray Gopal C.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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