Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-09-28
2001-04-24
Wiley, David A (Department: 2155)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C709S238000
Reexamination Certificate
active
06223242
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to crossbar switching configurations and more particularly to a linearly expandable self-routing crossbar switch and associated method. The invention is applicable in any multi-source/multi-destination digital switching application including the fields of computer networking and digital telecommunications switching.
A number of different applications present the need for a switching arrangement which may be configured for routing a flow of data from a particular port to any one of a number of other ports which are connected with the switching arrangement. In the prior art, such switching arrangements are generally referred to as crossbar switches.
FIG. 1
illustrates a four-port prior art crossbar switch, generally indicated by the reference numeral
10
, which is capable providing a data flow path between two selected ones of any of four ports A, B, C or D. While the arrangement of
FIG. 1
has proven to be effective for its intended use, it should also be appreciated that its capability for expansion is extremely limited.
FIG. 2
illustrates an overall crossbar switching arrangement, which is generally referred to by the reference numeral
20
, that is made up of four of the crossbar switching arrangements
10
a-d
originally shown in FIG.
1
. Arrangement
20
is configured for providing a data flow path between two selected ones of any of eight data ports A through H. While arrangement
20
serves its intended purpose, it should be appreciated that in order to double the number of ports served using the prior art four-port crossbar switch
10
of
FIG. 1
, the number of four-port crossbar switches
10
is multiplied by a factor of four.
As another example which is not illustrated, if sixteen ports (again doubling the number of ports) are to be served the number of prior art four-port crossbar switches would increase to sixteen. Thus, one of ordinary skill in the art should recognize that increasing the number of ports served results in a geometric increase in the required number of individual four-port cross-bar switches. This geometric expansion is particularly disadvantageous in terms of the hardware costs associated with expansion. Of course, a geometric expansion in terms of hardware results in a corresponding decrease in reliability of the overall switching arrangement. Another disadvantage stems from the fact that each additional layer of switches added to the overall arrangement adds latency (i.e., decreased data throughput based on time delays) in data routing operations.
The present invention solves the foregoing problems by providing a highly advantageous cross-bar switching arrangement which is expandable in a linear manner. An associated method is also provided.
SUMMARY OF THE INVENTION
As will be described in more detail hereinafter, there is disclosed herein a crossbar routing arrangement for use in a digital system having three or more buses. An associated method is also disclosed. This routing arrangement, like the crossbar switching arrangement of
FIG. 2
is configured for transferring a set of data received from any particular one of the buses to any other selected one of the buses. However, the routing arrangement of the present invention includes a control arrangement associated with each bus for dividing the set of data into at least first and second subsets of data and for adding self-routing signals to each data subset which signals identify the selected bus. A switching arrangement is configured for directing the first and second data subsets in a predetermined way responsive to the self-routing signals. First and second input data transfer paths are provided between the control arrangement associated with the particular bus and the switching arrangement such that the first data subset can be transferred from the particular bus to the switching arrangement using the first input data transfer path and the second data subset can be transferred from the particular bus to the switching arrangement using the second input data transfer path. In addition, first and second output data transfer paths connect the switching arrangement with the control arrangement associated with the selected bus such that the first data subset can be transferred from the switching arrangement to the selected bus using the first output data transfer path and so that the second data subset can be transferred from the particular bus to the switching arrangement using the second output data transfer path. The switching arrangement directs the first and second data subsets in the aforementioned predetermined way by transferring the first and second data subsets from the first and second input data transfer paths to the first and second output data transfer paths, respectively.
In accordance with one feature, the configuration of the routing arrangement provides for linear expansion whereby to service buses having increased width and/or to service an increased number of buses in a cost effective manner while, in either instance, maintaining high data throughput.
In one aspect of the present invention, the data transfer paths over which the data subsets are transferred are physically distinct paths.
In another aspect of the invention, the switching arrangement includes at least first and second switching units. Transfer of the data subsets from the particular bus to the selected bus is accomplished by routing the first data subset through the first switching unit and the second data subset through the second switching unit.
REFERENCES:
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patent: 5859975 (1999-01-01), Brewer et al.
patent: 5949982 (1999-09-01), Frankeny et al.
patent: 6035414 (2000-03-01), Okazawa et al.
patent: 6055599 (2000-04-01), Han et al.
F. Masetti and C. Raffaelli, Implementation Criteria for a High Speed Parallel Banyan Switch, 5/91, IEEE.
Setsuo Takahashi, Yasushi Fukuda, and Jun'ichirou Yanagi, Multi-Service ATM Node System, Aug. 1995, Hitachi Review, vol. 44, No. 4.
Nick McKeown et al, Tiny Tera: A Packet Switch Core, Jan./Feb. 1997, IEEE Micro.
Huie Jonathan L.
Koerner Christopher
Lincoln Bradford C.
Sheafor Stephen J.
Sugar Robert
Pritzkau Michael
Shear Stephen
Sifera, Inc.
Wiley David A
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