Variable performance ranking and modification in design for...
Variable sigma adjust methodology for static timing
Variable stage ratio buffer insertion for noise optimization...
Various methods and apparatuses to preserve a logic state...
Various methods and apparatuses to preserve a logic state...
Various methods and apparatuses to route multiple power...
VDHL/Verilog expertise and gate synthesis automation system
Vector interface to shared memory in simulating a circuit...
Vector interface to shared memory in simulating a circuit...
Vector Logic techniques for multilevel minimization
Vector logic techniques for multilevel minimization with...
Vector sequence simplification for circuit verification
Vectorless instantaneous current estimation
Vectorless instantaneous current estimation
Vendor independent method to merge coverage results for...
Verification apparatus, design verification method, and...
Verification equipment of semiconductor integrated circuit,...
Verification of 3D integrated circuits
Verification of an extracted timing model file
Verification of design blocks and method of equivalence...