Verification of 3D integrated circuits

Details Verification of 3D integrated circuits Verification of 3D integrated circuits

2008-06-18

2011-11-15

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Design of semiconductor mask or reticle

Layout generation

C716S100000, C716S106000, C716S110000, C716S119000

Reexamination Certificate

active

08060843

ABSTRACT:
A method of designing a 3D integrated circuit (3D IC) including providing a first layout corresponding to a first device of a 3D IC and a second layout corresponding to a second device of a 3D IC is provided. A verification, such as LVS or DRC, may be performed not only on each device separately, but may also be performed to ensure proper connectivity between devices. The verification may be performed on a single layout file (e.g., GDS II file) including the interface layer of the first and second die. Dummy feature pattern may be determined for the 3D IC using a layout including the interface layers of the first and second devices.

REFERENCES:
patent: 6415421 (2002-07-01), Anderson et al.
patent: 6925614 (2005-08-01), Lu et al.
patent: 2003/0237069 (2003-12-01), Mohan et al.
Chistinel Ababei et al., “Placement and Routing in 3D Integrated Circuits”, 10 pages. Research supported by DARPA under grant N66001-04-1-8909.
Singapore Office Action Dated Jun. 30, 2011; Application No. PIIE080275, 4 pages.

Affiliated with

Also associated with

Rating

Verification of 3D integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Verification of 3D integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Verification of 3D integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4272472