Using constraints in design verification

Using high-level language functions in HDL synthesis tools

Using local reduction in model checking to identify faults...

Using patterns for high-level modeling and specification of...

Using redundant routing to reduce susceptibility to single...

Using router feedback for placement improvements for logic...

Using selectable in-line inverters to reduce the number of...

Using standard pattern tiles and custom pattern tiles to...

Using transition time checks to determine noise problems on...

Utilizing multiple test bitstreams to avoid localized...

Validating continuous signal phase matching in high-speed...

Validating integrated circuits

Validating one or more circuits using one of more grids

Validating very large network simulation results

Validation of electrical performance of an electronic...

Variable clocked scan test improvements

Variable clocked scan test improvements

Variable design rule tool

Variable detail automatic invocation of transistor level...

Variable fill and cheese for mitigation of BEOL topography