Using patterns for high-level modeling and specification of...

Details Using patterns for high-level modeling and specification of... Using patterns for high-level modeling and specification of...

2005-11-17

2008-01-29

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07325209

ABSTRACT:
This invention is a high-level language to specify electronic system design patterns for functional verification. This invention includes automatic translation of the high-level language specification into assertion code from these patterns and temporal properties for design verification. This eliminates the need to code extra RTL to handle features such as pipelines and bus priorities. Such common features are specified only in high-level patterns and temporal properties to be verified. This is advantageous because less verification code to be written, automated synthesis of assertions enforces monitor-style of writing assertions rather than generator-style, and the high-level code can be seamlessly migrated to another verification tool by producing another code generator for the new assertion language.

REFERENCES:
patent: 2006/0117274 (2006-06-01), Tseng et al.

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