Simulator for the post-exposure bake of chemically amplified...
Simulator of dynamic circuit for silicon critical path debug
Simulator of semiconductor device circuit characteristic and...
Simulator-independent system-on-chip verification methodology
Simultaneous assignment of select I/O objects and clock I/O...
Simultaneous optimization of analog design parameters using...
Simultaneous parameter-driven and deterministic simulation...
Simultaneous path optimization (SPO) system and method
Simultaneous placement of large and small cells in an...
Simultaneously simulate multiple stimuli and verification...
Site control for OPC
Six-to-one signal/power ratio bump and trace pattern for...
Skeleton generation apparatus and method
Skew insensitive clocking method and apparatus
Skew lots for IC oscillators and other analog circuits
Skew-independent memory architecture
Slack sensitivity to parameter variation based timing analysis
Slack sensitivity to parameter variation based timing analysis
Slack sensitivity to parameter variation based timing analysis
Slack time analysis through latches on a circuit design