Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-01-03
2006-01-03
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06983431
ABSTRACT:
A method and system for the simultaneous placement of large and small cells in an electronic circuit. A coarse placement using well known methods may provide an initial placement of cells. Cells meeting a size criteria may be selected for further processing. An optimum cell orientation may be determined. An optimum axis of movement for separation may be determined. Overlapping cells may be separated and their positions may be optimized in both horizontal and vertical directions. Any cell moved from its initial placement may be fixed so as not to be moved during subsequent placements. This process may be repeated for cells meeting a new, generally smaller, size criteria. A well known detailed placement process may finalize a design. In this novel manner, large and small cells may be automatically simultaneously placed, deriving speed and quality advantages over prior art methods.
REFERENCES:
patent: 5801960 (1998-09-01), Takano et al.
patent: 5943243 (1999-08-01), Sherlekar et al.
patent: 6625792 (2003-09-01), Yamasaki
patent: 2003/0084418 (2003-05-01), Regan
Donelly Ross A.
Naylor William C.
Woolever Jason R.
Park Vaughan & Fleming LLP
Siek Vuthe
Synopsys Inc.
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