Skeleton generation apparatus and method

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000, C716S030000, C703S014000

Reexamination Certificate

active

07890911

ABSTRACT:
A skeleton generation method includes: creating a netlist which is a circuit connection information input file format for analog circuit simulation, as subcircuit descriptions corresponding to function blocks of a system, on the basis of input and output information on the function blocks; constructing a function block skeleton of a system level design language using the respective subcircuit descriptions as units of the function blocks, on the basis of the circuit connection information described in the netlist; and constructing a system skeleton on the basis of a result of analysis of connection information on nodes of the subcircuit descriptions.

REFERENCES:
patent: 5815402 (1998-09-01), Taylor et al.
patent: 6470478 (2002-10-01), Bargh et al.
patent: 4-42372 (1992-02-01), None
patent: 7-86886 (1995-03-01), None
patent: 7-306897 (1995-11-01), None
patent: 3033091 (2000-02-01), None
patent: 2003 16122 (2003-01-01), None
patent: 2004-220223 (2004-08-01), None

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