Skew-independent memory architecture

Details Skew-independent memory architecture Skew-independent memory architecture

1999-05-26

2002-05-21

Hoang, Huan (Department: 2818)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C365S233100, C365S189050

Reexamination Certificate

active

06393600

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates generally to the design of integrated circuits and the design thereof, and more particularly to a memory architecture and synthesis method using the memory architecture.
The use of integrated circuits is widespread and pervasive. Integrated circuits have a variety of uses, and are found in a variety of devices. Such integrated circuits often require temporary storage of information. Temporary storage of information allows integrated circuits to not only respond to immediate conditions, but to do so in view of past activities. The temporary storage of information is often accomplished using memory cells, and many integrated circuits include a large number of memory cells. In order to store information a particular memory cell must be specified for storage of the information, and the information must be provided to the memory cell. Thus, storage of information, or data, in a memory element, or cell, generally requires two separate signals. One signal, a selection signal, selects a particular memory element for storage of information, and another signal, a data signal, provides the information for storage in the particular memory element.
Further, the selection signal and the data signal used in storing data in a memory cell require a high degree of synchronization. Absent such synchronization, the particular memory cell may receive data intended for another memory cell, or the data intended for storage in the particular memory cell may, in fact, be stored in some other memory cell. The necessary degree of synchronization of the selection signal and the data signal is determined by a time period, a synchronization window, in which the selection signal and the data signal must both be valid with respect to each other. In general the synchronization window, that is the permissible variation in the timing of the selection and data signals, is determined by the clock period of a clock signal used within the integrated circuit, the clock skew between any two points within the integrated circuit, any signal skew in providing the signals, and any applicable circuit clement set-up and hold times. When the clock period is relatively long, the various skews and set-up and hold times are somewhat irrelevant. As the clock period decreases, however, the synchronization requirement becomes more exacting and variations introduced, for example, by data signal and clock signal travel paths, may introduce skews of importance.
For many modern integrated circuits, which operate at high clock speeds, the clock period is sufficiently short that clock skew and signal skew may affect synchronization of the selection and data signals. Accordingly, great care must be taken in the placement of memory elements and the routing of data and clock signals to ensure sufficient synchronization of signals. Absent great care in the placement of circuitry for generating selection signals and placement of circuitry for generating data signals, operation of the integrated circuit as a whole may be faulty.
In addition, layout space in modern integrated circuits is often at a premium as integrated circuits are performing ever increasing tasks and have ever increasing capabilities without commensurate increases in chip size. Thus, placement of circuitry associated with memory elements must also be done with a view to minimizing layout space of the integrated circuit as a whole, which can be a difficult task due to the numerous elements which make up the integrated circuit.
Preferably, placement of circuitry associated with memory elements would be performed automatically by tools, such as place and route tools. Place and route tools automatically arrange and interconnect logic cells on a chip, based on the size of the logic cells, the footprint of the chip, timing requirements provided by the designers, and other criteria. Place and route tools, however, do have limitations. For example, place and route tools often are unable to tightly pack components, and place and route tools often require that signals upon which timing criteria are based be proximately tied to a clock signal. The circuitry generating the selection signal and the data signal, however, must be tightly packed to meet timing requirements, and the signals, particularly the data signal, are often not proximately tied to a clock signal. Thus, place and route tools are often unable to accurately determine placement requirements of circuitry associated with generating selection and data signals as entities separate from the memory element.
Accordingly, laborious and exacting “hard-placement,” i.e., explicit selection of location of memory elements and associated circuitry within the integrated circuit, is required to be performed by the designer. In other words, the designer hand places the memory element, the circuit elements generating the selection signal, and the circuit elements generating the data signal with respect to each other in a tightly packed manner. Together these tightly packed elements form a specially handled block.
FIG. 1
illustrates a block diagram of a specially handled block, with a specially handled block
10
responsive to a write enable signal
11
, a clock signal
12
, an address bus
13
, and a write data signal
14
.
The specially handled block
10
includes circuitry corresponding to that of FIG.
2
.
FIG. 2
illustrates circuitry for providing temporary storage of information, i.e., a memory architecture. A memory cell
37
is used to store information. More than one memory cell may be present, but for clarity only one memory cell is shown. The memory cell is selected using a word line signal
52
, and receives data via a data signal
58
. The word line signal is generated using a write enable signal, a clock signal, and an address bus. The write enable signal indicates that a write operation, opposed to a read operation, is to occur. The clock signal provides a timing reference for circuit operation. The address bus provides information as to which particular memory cell is subject to the operation. As the write is to occur when both the clock signal and the write enable signal are low, the write enable signal and the clock signal are provided to a two input NOR gate
31
. The output of the NOR gate
31
supplies a first input to an AND gate
35
. A second input to the AND gate
35
is an address selected signal that is produced by an address decoder
33
. The address decoder responds to input of address information from the address bus. Thus, the second input to the NOR gate indicates selection of the memory cell for an operation. The AND gate
35
produces the word line signal for the memory cell. The second input into the memory cell
37
is the data signal. The data signal is formed by a buffer
39
. The buffer
39
receives a write data signal as its input. In
FIG. 2
, the storing of the data signal in the memory cell
37
is accomplished using the buffer
39
. The selection of the memory cell
37
is accomplished by the NOR gate
31
, AND gate
35
and the address decoder
33
.
The use of hand-placed specially handled blocks, such as the specially handled block of
FIG. 1
, presents several problems, however. Place and route tools must still connect the specially handled blocks to other components, and such connections may result in chip area wastage as the place and route tool is unable to locate the hand-placed specially handled block and the connections to the specially handled block in an optimum manner. More importantly, as chip complexity increases so does the number of specially handled blocks. Large numbers of specially handled blocks simply cannot be manually placed in an economic or efficient manner. Even more importantly, specially handled blocks are, by their very nature, adapted for use with a specific process technology, such as a 0.25 micron or 0.18 micron technology. The delay calculations, space requirements,. power requirements, and other considerations for components making up the specially handled block are determined with respect to a specific tec

Affiliated with

Also associated with

Rating

Skew-independent memory architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Skew-independent memory architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Skew-independent memory architecture will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2838251