Skew insensitive clocking method and apparatus

Details Skew insensitive clocking method and apparatus Skew insensitive clocking method and apparatus

2005-04-01

2009-12-15

Levin, Naum B (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C327S153000, C327S155000, C327S202000, C713S400000, C714S731000

Reexamination Certificate

active

07634749

ABSTRACT:
A method of designing a skew insensitive circuit is performed by designing a synchronous circuit including flip-flops and combinatorial logic and, for each flip-flop, inserting logic gates to receive a skewed clock signal and to locally derive non-overlapping clock phases from the skewed clock signal.

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