Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-06-13
2006-06-13
Whitmore, Stacy A. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07062734
ABSTRACT:
Slack times at an input of a latch in a circuit design are determined by determining a set of required times at the input of the latch, where the set of required times includes a required time entry for each different relationship between a signal comprising a downstream event and a clock signal for the latch. A set of arrival time entries at the input of the latch is also determined, each arrival time entry having a corresponding required time entry.
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Klarquist & Sparkman, LLP
Levin Naum B
Whitmore Stacy A.
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