Simulator of dynamic circuit for silicon critical path debug

Details Simulator of dynamic circuit for silicon critical path debug Simulator of dynamic circuit for silicon critical path debug

2002-04-01

2004-07-06

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06760891

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to determining operating characteristics of integrated circuit chips, and more particularly to determining the operating characteristics of dynamic circuits within integrated circuit chips.
2. Description of the Related Art
Digital logic circuits are implemented using various electronic technologies. Commonly used electronic technologies include metal oxide semi-conductor (MOS) technology, particularly complimentary MOS (CMOS) technology. CMOS technology is common in static circuits.
FIG. 1A
shows a circuit diagram of a static CMOS transistor circuit, specifically a logical NAND gate. An input A
100
and input B
105
are received by the circuit. Only if input A
100
and input B
105
are high (i.e., both have values of “1”) is the value at output OUT
100
low (i.e., a value of “0”). All other input conditions to input A
100
and input B
105
result in a high output value.
Although designed initially for static circuits, CMOS technology has been implemented into dynamic circuits. Dynamic circuits essentially operate in conjunction with a clock pulse signal.
FIG. 1B
is a diagram illustrating a dynamic circuit, specifically a logical NAND gate. An input A
120
and input B
125
along with a clock signal
130
are received by the circuit. Only if input A
120
, input B
125
, and the clock signal
130
are high is OUT
135
low. When the clock signal
130
is low, output OUT
135
is high regardless of the state of input A
120
and of input A
130
. However, in a dynamic circuit OUT is only valid when the clock is high. When the clock signal is high and either or both input A
120
and input B
130
is low, then the output OUT is high.
Dynamic circuits are faster than static circuits because dynamic circuits allow setting up gates in a cascade or domino arrangement. Information arrives down the cascade of gates at full speed, similar to a row of falling dominos. For cascaded gates no stage transition can occur until any predecessor stage transition occurs. For dynamic circuits, when the clock signal is high, the clock signal is considered to be in “evaluation phase.” When the clock signal is low, the clock signal is considered to be in “pre-charged phase.” By having a pre-charge phase set to low, multiple circuits or logic stages can use a single clock signal. A common clock signal is used by a number of circuits, sub-systems, systems, and devices.
For a dynamic circuit to properly operate, falling edge transitions are not allowed for any gate inputs during the evaluation phase. Such a transition will potentially generate an error in the dynamic circuit, and can lead to an error in the system or device in which the dynamic circuit resides. Since clock frequencies relate to the number of times per second a clock pulse switches from high (evaluation phase) to low (pre-charge phase), relatively lower frequencies allow sufficient time for the input to settle before the dynamic circuit enters the evaluation phase. As operating frequency is increased, the likelihood of experiencing the transitioning problem also increases as these transitions are unable to settle before the available clock arrives, violating the input setup time of the dynamic circuit and eventually reaching an operating frequency where the dynamic circuit can not operate.
Integrated circuit (IC) chips can contain a number of static and dynamic circuits. IC chips can also be part of a larger system or device. Once an IC chip is fabricated into silicon, a thorough understanding of the interrelationship between intra-chip, intra-system, and intra-device signals is desirable. An important step in the understanding of the interrelationship involves debugging a particular dynamic circuit and understanding critical path and critical clock frequencies affecting the dynamic circuit.
When various circuits and systems depend upon inputs and provide outputs to other dynamic circuits and static circuits, determining circuit behavior, in particular operating frequency is important in troubleshooting and debugging of systems, specifically IC chips.
Determining the maximum frequency in which an IC chip can operate depends on at what frequencies circuits within the IC chip can functionally operate. Typically, guesses are made as to the critical frequencies and critical paths that relate to dynamic circuits. Further, when IC chips are integrated into larger systems, failure analysis becomes important in determining causes or potential causes of failures of subsystems, devices, or circuits of the larger system.
SUMMARY OF THE INVENTION
Accordingly, accurately, effectively, and quickly identifying the silicon behavior of dynamic circuit when the setup time to the dynamic circuit input is violated is desirable. An abstract register transfer level (RTL) model that simulates behavior of a dynamic circuit is created. The model is built upon an existing RTL with another level of abstraction capturing input transitions.
In one embodiment, the invention relates to modeling a dynamic circuit. The modeling determines a previous input value, a next input value and combines the previous input value and the next input value to generate a modeled input value. The modeling additionally models an expected output value based upon the modeled input value.
In another embodiment, the invention relates to modeling a dynamic circuit. The modeling determines first and second previous input and output values. The modeling combines a first previous input value and the first next input value to generate a first modeled input value. Additionally, the modeling combines a second previous input value and a second next input value to generate a second modeled input value. The modeled first and second expected output values are based upon the first and second modeled input values.
In another embodiment, the invention relates to troubleshooting a circuit in an integrated circuit chip. The simulation model includes predicted operational characteristics of the circuit. The operational characteristics include operating frequency values. The simulation model determines a previous input value and a next input value. The previous input value and the next input value are combined to generate a modeled input value. The expected output value is based upon the modeled input value. The circuit is tested under increasing frequency values until an error is seen. Operational characteristics are recorded and include operating frequency of the integrated circuit chip when the error is seen. The predicted operational characteristics are compared with the recorded operational characteristics.
In another embodiment, the invention relates to an apparatus for modeling the operation of a dynamic circuit which comprises means for determining a previous input value and a next input value. The previous input value and the next input value are combined to generate a modeled input value. An expected output value is based upon the modeled input value.
The foregoing is a summary and thus contains, by necessity, simplifications, generalizations and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting. Other aspects, inventive features, and advantages of the present invention, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth below.


REFERENCES:
patent: 6195776 (2001-02-01), Ruiz et al.
patent: 6594800 (2003-07-01), Chang et al.

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