Implementing enhanced wiring capability for electronic...

Implementing hierarchical design-for-test logic for modular...

Implementing memory read data eye stretcher

Implementing method for buffering devices

Implementing programmable logic array embedded in...

Impurity concentration distribution predicting method and...

Impurity quantity transfer device enabling reduction in...

In situ wafer heat for reduced backside contamination

In-circuit device, system and method to parallelize design...

In-line XOR checking of master cells during integrated...

In-place method for inserting repeater buffers in an...

In-place repeater insertion methodology for over-the-block...

In-plane distribution data compression method, in-plane...

Inclusion of global wires in capacitance extraction

Incorporation of uncertainty information in modeling a...

Incorporation of uncertainty information in modeling a...

Increased effective flip-flop density in a structured ASIC

Increasing scan compression by using X-chains

Incremental concurrent processing for efficient computation...

Incremental design reduction via iterative overapproximation...