Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-10-16
2007-10-16
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
10970727
ABSTRACT:
Systems and methods for verifying integrated circuit designs: (a) receive input corresponding to physical layouts of cells of the design and available master cells. The systems and methods then determine if the design cells are intended to correspond to one of the master cells, and if so, the systems and methods then determine if the layouts of the cells and the corresponding master cells match one another, e.g., by a layout vs. layout comparison of the design cell with the master cell to determine if the coordinates of the polygon(s) in the design cell match corresponding coordinates of the polygon(s) in the master cell. An “XOR” comparison may be used to determine if the design cell features match the corresponding master cell features. Computer-readable media may be adapted to include computer-executable instructions for performing such methods and operating such systems.
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Ferguson John G.
LeBritton Joseph Andrew
Bowers Brandon W.
Chiang Jack
Kaplan Jonathan T.
Mentor Graphics Corporation
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