Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-11-22
2005-11-22
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06968525
ABSTRACT:
An implementing method for buffering devices is provided, so as to dispose the buffering devices on a chip. The chip includes a signal source root and the number X of output bonding pads, in which the number X is a positive integer. The implementing method of the present invention includes (a) implementing a buffering device for the Nthlayer at a location close to the middle place between two output bonding pads, and electrically connecting each one of the output bonding pads to the corresponding one of the buffering devices for the Nthlayer, respectively. (b) A buffering device for the N+1thlayer is implemented at a location close to the middle place between two buffering devices for the Nthlayer, and each one of the buffering devices for the Nthlayer is electrically connected to the corresponding one of the buffering devices for the N+1thlayer, respectively. Then, the number of the buffering devices for the N+1thlayer is judged whether or not to be 1. If it is, then the buffering device for the N+1thlayer is connected to the signal source root and the method goes to end. If it is not, the method goes to the step (c). In the step (c), the quantity of the parameter N is added by 1, and then the method repeatedly performs the step (b).
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Chang Yung-Chung
Chiu You-Ming
Levin Naum
Rabin & Berdo P.C.
Smith Matthew
VIA Technologies Inc.
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