Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-06-07
2011-06-07
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S136000, C714S030000, C714S726000, C714S733000, C714S734000, C714S738000
Reexamination Certificate
active
07958472
ABSTRACT:
To increase scan compression during testing of an IC design, an X-chain method is provided. In this method, a subset of scan cells that are likely to capture an X are identified and then placed on separate X-chains. A configuration and observation modes for an unload selector and/or an unload compressor can be provided. The configuration and observation modes provide a first compression for non-X-chains that is greater than a second compression provided for X-chains. ATPG can be modified based on such configuration and observation modes. This X-chain method can be fully integrated in the design-for-test (DFT) flow, requires no additional user input, and has negligible impact on area and timing. Test generation results on industrial designs demonstrate significantly increased compression, with no loss of coverage, for designs with high X-densities.
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Kanzawa Yasunari
Neuveux Frederic J.
Waicukauski John A.
Wohl Peter
Bever Hoffman & Harms LLP
Harms Jeanette S.
Kik Phallaka
Synopsys Inc.
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