Increasing scan compression by using X-chains

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing

Reexamination Certificate

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C716S136000, C714S030000, C714S726000, C714S733000, C714S734000, C714S738000

Reexamination Certificate

active

07958472

ABSTRACT:
To increase scan compression during testing of an IC design, an X-chain method is provided. In this method, a subset of scan cells that are likely to capture an X are identified and then placed on separate X-chains. A configuration and observation modes for an unload selector and/or an unload compressor can be provided. The configuration and observation modes provide a first compression for non-X-chains that is greater than a second compression provided for X-chains. ATPG can be modified based on such configuration and observation modes. This X-chain method can be fully integrated in the design-for-test (DFT) flow, requires no additional user input, and has negligible impact on area and timing. Test generation results on industrial designs demonstrate significantly increased compression, with no loss of coverage, for designs with high X-densities.

REFERENCES:
patent: 6463561 (2002-10-01), Bhawmik et al.
patent: 7278123 (2007-10-01), Ravi et al.
patent: 7284176 (2007-10-01), Wang et al.
patent: 7302624 (2007-11-01), Rajski et al.
patent: 7353470 (2008-04-01), Cooke et al.
patent: 7412672 (2008-08-01), Wang et al.
patent: 7415678 (2008-08-01), Gizdarski
patent: 7437640 (2008-10-01), Rajski et al.
patent: 7509550 (2009-03-01), Rajski et al.
patent: 7647540 (2010-01-01), Rajski et al.
patent: 7721172 (2010-05-01), Wang et al.
patent: 7725849 (2010-05-01), Abercrombie et al.
patent: 7735049 (2010-06-01), Wang et al.
patent: 7823034 (2010-10-01), Wohl et al.
patent: 7823035 (2010-10-01), Litten et al.
patent: 7865849 (2011-01-01), Butler et al.
patent: 2006/0041812 (2006-02-01), Rajski et al.
patent: 2006/0041813 (2006-02-01), Rajski et al.
patent: 2006/0041814 (2006-02-01), Rajski et al.
patent: 2007/0143718 (2007-06-01), Abercrombie et al.
patent: 2008/0256497 (2008-10-01), Wohl et al.
patent: 2008/0294953 (2008-11-01), Cheng et al.
patent: 2009/0177936 (2009-07-01), Koenemann et al.
patent: 2009/0210830 (2009-08-01), Butler et al.
patent: 2009/0249147 (2009-10-01), Rajski et al.
patent: 2010/0017760 (2010-01-01), Kapur et al.
Ferhani et al.: “Classifying Bad Chips and Ordering Test Sets”, 2006 IEEE, International Test Conference, Lecture 1.2, pp. 1-10.
Wohl et al.: “Fully X-Tolerant Combinational Scan Compression”, 2007 IEEE, International Test Conference, Paper 6.1, pp. 1-10.
Sharma et al.: “X-Filter: Filtering Unknowns From Compacted Test Responses”, 2005 IEEE, International Test Conference, Paper 42.1, pp. 1-9.
Wohl et al.: “Design Of Compactors for Signature-Analyzers in Built-In Self Test”, ITC International Test Conference, 2001 IEEE, Paper 3.1, pp. 54-63.
Mitra et al.: “X-Compact an Efficient Response Compaction Technique for Test Cost Reduction”, ITC International Test Conference, 2002 IEEE, Paper 11.2, pp. 311-320.
Mitra et al.: “X-Tolerant Signature Analysis”, ITC International Test Conference, 2004 IEEE, Paper 15.1, pp. 432-441.
Keller et al.: “An Economic Analysis And ROI Model For Nanometer Test”, ITC International Test Conference, 2004 IEEE, Paper 18.1, pp. 518-524.
Vermeulen et al.: “Trends in Testing Integrated Circuits”, ITC International Test Conference, 2004 IEEE, Paper 24.2, pp. 688-697.
Wohl et al.: “X-Tolerant Compression and Application of Scan-ATPG Patterns in a BIST Architecture”, ITC International Test Conference, 2003 IEEE, Paper 29.1, pp. 727-736.
Rajski et al.: “Convolutional Compaction of Test Responses”, ITC International Test Conference, 2003 IEEE, Paper 29.3, pp. 745-754.
Wohl et al.: “Minimizing the Impact of Scan Compression”, Proceedings of the IEEE VLSI Test Symposium, May 2007, 8 pages.
Patel et al.: “Application of Saluja-Karpovsky Compactors to Test Responses With Many Unknowns”, Proceedings of the IEEE VLSI Test Symposium, May 2003, 7 pages.
Rajski et al.: “Synthesis of X-Tolerant Convolutional Compactors”, Proceedings of the IEEE VLSI Test Symposium, May 2005, 6 pages.
Wohl et al.: “Analysis and Design of Optimal Combinational Compactors”, Proceedings of the IEEE VLSI Test Symposium, May 2003, 7 pages.

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