Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-07-10
2008-12-02
Lin, Sun J (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07461365
ABSTRACT:
An H-tree is formed in a conducting layer over a base array of a structured ASIC, an H-tree being a predefined constraint imposed on ad hoc circuit designs adapted to make use of the base array and H-tree. The endpoints of the H-tree are formed at or near sequential elements. When the H-tree is used as part of a clock structure, clock skew to the sequential elements is minimized as is the consumption of routing resources for forming the clock structure. When a pulse generator is coupled to the H-tree, each individual flip-flop of a plurality of flip-flops can be emulated with an individual latch, thereby increasing effective flip-flop density.
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Galbi David
West Eric T.
Dyke Korbin Van
Lightspeed Logic, Inc.
Lin Sun J
PatentVentures
Smith Bennett
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