Estimating LUT power usage
Estimating quality during early synthesis
Estimating the difficulty level of a formal verification...
Evaluating a validation vector for validating a network design
Evaluation device and circuit design method used for the same
Evaluation device and circuit design method used for the same
Evaluation method for interconnects interacted with...
Evaluation method of semiconductor device, manufacturing...
Evaluation of a technology library for use in an electronic...
Evaluation of the design quality of network nodes
Evaluation TEG for semiconductor device and method of...
Evaluation TEG for semiconductor device and method of...
Event-based temporal logic
Evolutionary programming of configurable logic devices
Evolutionary technique for automated synthesis of electronic...
Exact geometry operations on shapes using fixed-size integer...
Exploiting suspected redundancy for enhanced design...
Exploiting unused configuration memory cells
Exponential increments in FET size selection
Exposing method and apparatus for semiconductor integrated...