Evaluation method for interconnects interacted with...

Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Analysis and verification

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S136000

Reexamination Certificate

active

08001492

ABSTRACT:
A design and evaluation method for interconnect wires of integrated circuits is provided to detect, analyze and predict response of interconnect layout to integrated-circuit manufacture processes.

REFERENCES:
patent: 6057171 (2000-05-01), Chou et al.
patent: 6304097 (2001-10-01), Chen
patent: 7111257 (2006-09-01), Robson et al.
patent: 7434197 (2008-10-01), Dolainsky et al.
patent: 7644388 (2010-01-01), Daldoss et al.
patent: 7653519 (2010-01-01), Overhauser
patent: 7653888 (2010-01-01), Habib et al.
patent: 7730434 (2010-06-01), Aghababazadeh et al.
patent: 7747978 (2010-06-01), Ye et al.
patent: 7790340 (2010-09-01), Progler

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Evaluation method for interconnects interacted with... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Evaluation method for interconnects interacted with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Evaluation method for interconnects interacted with... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2795150

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.