Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Analysis and verification
Reexamination Certificate
2011-08-16
2011-08-16
Garbowski, Leigh Marie (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
Analysis and verification
C716S136000
Reexamination Certificate
active
08001492
ABSTRACT:
A design and evaluation method for interconnect wires of integrated circuits is provided to detect, analyze and predict response of interconnect layout to integrated-circuit manufacture processes.
REFERENCES:
patent: 6057171 (2000-05-01), Chou et al.
patent: 6304097 (2001-10-01), Chen
patent: 7111257 (2006-09-01), Robson et al.
patent: 7434197 (2008-10-01), Dolainsky et al.
patent: 7644388 (2010-01-01), Daldoss et al.
patent: 7653519 (2010-01-01), Overhauser
patent: 7653888 (2010-01-01), Habib et al.
patent: 7730434 (2010-06-01), Aghababazadeh et al.
patent: 7747978 (2010-06-01), Ye et al.
patent: 7790340 (2010-09-01), Progler
Garbowski Leigh Marie
Linden Design Technologies, Inc.
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