Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-03-20
2003-06-03
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06574789
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an exposing method and apparatus for semiconductor integrated circuits, or large scale integration (“LSI”), and particularly to a method of generating exposing patterns and, in detail, a method of rating exposing patterns and an exposing apparatus including a dummy pattern generating process and a dummy pattern adding process.
2. Description of the Related Art
Recently, high-density and high-integration structures of semiconductor integrated circuits have been realized by utilizing a multilayer wiring technique in which two or more wiring layers are laid. In such multilayer wiring structures, a structure including a large stepped area can be easily generated and, thus, a flat semiconductor wafer is hard to attain. Therefore, wiring may be easily areas will cause pattern resolution failure because the light beam is never set within the focal depth during the exposing process. Therefore, a method is proposed, in view of alleviating the stepped area, where the pattern density is uniform and the semiconductor wafer is flat by using dummy patterns, which are electrically independent and do not function as an actual circuit. The dummy patterns are generated in an area where the pattern density is rather low and, then, the dummy patterns and other the other patterns are combined.
FIG. 8
illustrates a prior art method for generating dummy patterns and then merging them to the design patterns. In
FIG. 8
, numeral
30
designates a design pattern;
31
, dummy pattern data;
32
, an exposing pattern;
33
, a reticle inspection pattern; and
34
, a reticle, mask or wafer after exposing or inspection. Moreover, the figure in the shape of the letter “F” in
FIG. 8
schematically indicates patterns forming a circuit and small rectangular shapes of the same pattern are dummy patterns.
In the flow of the process shown in
FIG. 8
, the design pattern
30
, generated by the design process, and dummy pattern data
31
, generated based on the design pattern
30
, are merged (ORed) to form one synthesized pattern and the exposing pattern
32
is generated from this synthesized pattern through various data processes. Based on the exposing pattern
32
, the process of exposing the reticle, mask or wafer is executed to finally manufacture the reticle, mask or wafer
34
. On the other hand, the reticle inspection pattern
33
is generated from the same exposing pattern data
32
and inspection of reticle
34
is executed based on the reticle inspection pattern
33
.
Next, the process for generating the dummy pattern
31
based on the design pattern
30
illustrated in FIG.
8
and the process for merging the generated dummy pattern
31
and design pattern
30
will be explained in detail with reference to FIGS.
9
(
a
)-
9
(
g
). Here, the design patterns are illustrated on the left-hand side of this figure, while the dummy patterns for the generation process are illustrated in the right-hand side.
First, FIG.
9
(
a
) shows the initial status. The design patterns illustrated here are the wiring patterns
40
having two vertical lines. Meanwhile, the dummy patterns are not yet generated.
Next, in FIG.
9
(
b
), the dummy patterns
41
, made of small rectangles of the same shape, are generated regularly throughout the entire area. In this case, for example, when a “dummy rule” is 1.0&mgr;, dummy patterns of 1.0&mgr; squared are generated in every 1.0&mgr; interval, namely, one dummy pattern is generated in every 4 &mgr;m squared. If the actual size of a device element is 15.5 mm×15.5 mm, the dummy pattern generation area will be as wide as 5 times the actual size of the device element, namely 77.5 mm×77.5 mm. Therefore, the number of dummy patterns to be generated in this area is about 1.5×10
9
((77500×77500)/4). When the amount of data required for one dummy pattern is assumed to be 5 bytes, an amount of data as high as 7.5×10
9
bytes is required for all dummy patterns. Moreover, when the “dummy rule” is 2.0&mgr;, dummy patterns of 2.0&mgr; squared are generated at an interval of every 2.0&mgr;, namely, the number of dummy patterns to be generated in this area is about 3.8×10
8
[77500×77500]/16] and the number of bytes required for all dummy patterns reaches 1.9×10
9
bytes.
In FIG.
9
(
c
), information about the design patterns
40
is read and then artificially overlapped onto the dummy pattern
41
(hereinafter referred to as artificially overlapped design patterns
42
). In FIG.
9
(
d
), the artificially overlapped design patterns
42
are shifted outwardly as much as the mutual interval between the dummy patterns
41
and design patterns
40
, which causes the pattern shape to widen. In FIG.
14
(
e
), some data comprising the dummy patterns
41
and shifted artificially overlapped design patterns
44
are merged to remove the parts exposed multiple times. With the process explained above, the unwanted area in which the dummy patterns
41
and the artificially overlapped design patterns
44
are overlapped can be removed. In FIG.
14
(
f
), the artificially overlapped design patterns
44
are removed from the data and the remaining data is defined as the dummy patterns
45
, which depend on the design patterns on the left-hand side of the figure. Finally, in FIG.
14
(
g
), the dummy patterns
45
generated in the preceding step and the original design patterns
40
are merged.
However, the conventional method for dummy pattern generation explained above has a problem in that a large amount of dummy patterns are added in addition to a large amount of design patterns and, thereby, the total amount of data is greatly increased. If the design patterns in the initial stage when generating the exposing patterns already contains a large amount of data, the processing time is increased to a large extent for the subsequent processes, namely, in the process to convert the design patterns to the exposing patterns or to the patterns for the inspection apparatus. Moreover, as the computer load increases, the occurrence of problems such as defective computer operations also increases.
Therefore, it is an object of the present invention to overcome the problems explained above. A further object of this invention is to provide a method of executing the exposing process and inspection process by adding the dummy patterns to the design patterns without the need to process large amounts of data for a series of exposing pattern generation processes.
SUMMARY OF THE INVENTION
It is an object of the present invention to overcome the above-described problems of the prior art by exposing semiconductor integrated circuits by inputting exposing pattern data to an exposing apparatus and extracting exposing pattern data for every predetermined unit area from the exposing pattern data and merging the extracted exposing pattern data and dummy pattern data for every unit area identical to the predetermined unit area and exposing the merged exposing pattern data and dummy pattern data for every predetermined unit area.
It is another object of the present invention to overcome the above-described problems in the prior art by an apparatus for exposing patterns of a semiconductor integrated circuit device in a semiconductor integrated circuit manufacturing apparatus, having a first memory for storing exposing pattern data extracted for every predetermined unit area and a second memory for storing dummy pattern data for every predetermined unit area and dummy pattern generation calculating unit for synthesizing the dummy pattern data input from the second memory to the exposing pattern input from the first memory.
According to this manufacturing apparatus, since the dummy patterns are generated in the exposing apparatus for every unit area of the exposing process, an amount of data of the exposing pattern to be processed by the exposing apparatus can be reduced and, thereby, a high speed exposing pattern data generating process can be realized and the load of the compu
Fujitsu Limited
Smith Matthew
Staas & Halsey , LLP
Thompson A. M.
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