Spare cells placement methodology
Spatial characteristic and logical hierarchy based manner...
Spatial signature analysis
Special engineering change order cells
Special tie-high/low cells for single metal layer route changes
Specification of the hierarchy, connectivity, and graphical...
Specification window violation identification with...
Specimen analyzing method
Speed verification of an embedded processor in a...
Speeding up timing analysis by reusing delays computed for...
SPICE simulation system for diode and method of simulation...
Spice to verilog netlist translator and design methods using...
Spine selection mode for layout editing
Split and merge design flow concept for fast turnaround time...
Split I/O circuit for performance optimization of digital...
Stability metrics for placement to quantify the stability of...
Stackable motherboard and related sensor systems
Standard block architecture for integrated circuit design
Standard cell design incorporating phase information
Standard cell for a CAD system