Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-06-12
2007-06-12
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C714S726000, C714S732000, C714S733000
Reexamination Certificate
active
10837395
ABSTRACT:
Method and apparatus for generating a test program for a programmable logic device having an embedded processor. Predetermined code is obtained to exercise at least one speed limiting path identified. To the predetermined code is added wrapper code to provide the test program, the wrapper code in part for loading the predetermined code into cache of the embedded processor for testing the at least one speed limiting path of the embedded processor identified.
REFERENCES:
patent: 3761695 (1973-09-01), Eichelberger
patent: 4687988 (1987-08-01), Eichelberger et al.
patent: 4880754 (1989-11-01), Correale
patent: 5307478 (1994-04-01), Rasbold et al.
patent: 5719783 (1998-02-01), Kerzman et al.
patent: 5724250 (1998-03-01), Kerzman et al.
patent: 5748497 (1998-05-01), Scott et al.
patent: 5761515 (1998-06-01), Barton, III et al.
patent: 5819072 (1998-10-01), Bushard et al.
patent: 5852712 (1998-12-01), Allen et al.
patent: 5889788 (1999-03-01), Pressly et al.
patent: 5923564 (1999-07-01), Jones, Jr.
patent: 5963566 (1999-10-01), Rajsuman et al.
patent: 6035407 (2000-03-01), Gebara et al.
patent: 6059451 (2000-05-01), Scott et al.
patent: 6071003 (2000-06-01), Ashuri et al.
patent: 6133582 (2000-10-01), Osann et al.
patent: 6154872 (2000-11-01), Jones
patent: 6163875 (2000-12-01), Suzuki
patent: 6185714 (2001-02-01), Satoh
patent: 6212666 (2001-04-01), Gohl et al.
patent: 6249893 (2001-06-01), Rajsuman et al.
patent: 6314540 (2001-11-01), Huott et al.
patent: 6363520 (2002-03-01), Boubezari et al.
patent: 6408412 (2002-06-01), Rajsuman
patent: 6415403 (2002-07-01), Huang et al.
patent: 6424583 (2002-07-01), Sung et al.
patent: 6427224 (2002-07-01), Devins et al.
patent: 6513103 (2003-01-01), Garlepp et al.
patent: 6532571 (2003-03-01), Gabrielson et al.
patent: 6609228 (2003-08-01), Bergeron et al.
patent: 6657635 (2003-12-01), Hutchins et al.
patent: 6658506 (2003-12-01), Nassif et al.
patent: 6658610 (2003-12-01), Chai et al.
patent: 6658633 (2003-12-01), Devins et al.
patent: 6817006 (2004-11-01), Wells et al.
patent: 6826717 (2004-11-01), Draper et al.
patent: 6839874 (2005-01-01), Fang
patent: 6874108 (2005-03-01), Abramovici et al.
patent: 6891410 (2005-05-01), Sadowski
patent: 6934922 (2005-08-01), Burnley
patent: 6973636 (2005-12-01), Shin et al.
patent: 6983405 (2006-01-01), Herron et al.
patent: 7007251 (2006-02-01), Hekmatpour
patent: 7017094 (2006-03-01), Correale et al.
patent: 7062744 (2006-06-01), Osann
patent: 7080300 (2006-07-01), Herron et al.
patent: 7092865 (2006-08-01), Burnley et al.
patent: 2002/0075740 (2002-06-01), Sung et al.
patent: 2003/0105617 (2003-06-01), Cadambi et al.
patent: 2003/0167144 (2003-09-01), Wang et al.
patent: 2003/0177455 (2003-09-01), Kaufman et al.
patent: 2004/0006584 (2004-01-01), Vandeweerd
patent: 2004/0025129 (2004-02-01), Batchelor
patent: 2004/0027462 (2004-02-01), Hing
patent: 2004/0030861 (2004-02-01), Plackle et al.
patent: 2004/0040005 (2004-02-01), Carison
patent: 2004/0061541 (2004-04-01), Correale et al.
patent: 2004/0062360 (2004-04-01), Holeva
patent: 2004/0064771 (2004-04-01), Appinger et al.
patent: 2004/0064794 (2004-04-01), Yang
patent: 2004/0133830 (2004-07-01), Lee
patent: 2004/0151209 (2004-08-01), Cummings et al.
patent: 2004/0216061 (2004-10-01), Floyd et al.
patent: 2005/0102594 (2005-05-01), Dey et al.
patent: 2005/0154552 (2005-07-01), Stroud et al.
patent: 2005/0160402 (2005-07-01), Wang et al.
patent: 2005/0188230 (2005-08-01), Bilak
patent: 2005/0278680 (2005-12-01), Mukherjee
patent: 2006/0119397 (2006-06-01), Ferraiolo et al.
Xilinx, Inc.; “Virtex-II Prox X Platform FPGAs: Functional Description”; DS110-2 (v1.1); Advance Product Specification; Mar. 5, 2004; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 1-51.
Xilinx, Inc.; “Processor Local Bus (PLB) Arbiter Design Specification”; Virtex-II Pro IP Handbook; Feb. 27, 2002; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 35-70.
Xilinx, Inc.; “PLB Block RAM (BRAM) Interface Controller”; DS420 (v1.2); Product Specification; Nov. 11, 2002; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 525-534.
Marion G. Harman et al.; “A Retargetable Technique for Predicting Execution Time of Code Segments”; This work was supported in part by grants from the U.S. Office of Nayal Research; pp. 1-30. Best available date for the examination purpose is the date of filing instant IDS is Aug. 11, 2004.
Jay Lawrence; “Orthogonality of Verilog Data Types and Object Kinds”; Cadence Design Systems; Copublished by the IEEE CS and the IEEE CASS; IEEE Design and Test of Computers; Copyright 2003 IEEE, pp. 94-96.
Interview; “ARM Twisting with Sir Robin, An Interview with ARM Chairman Sir Robin Saxby”; Copyright 2003 IEEE; Copublished by the IEEE CS and the IEEE CASS; IEEE Design and Test of Computers; pp. 90-93.
Peter C. Maxwell; “Wafer-Package Test Mix for Optimal Defect Detection and Test Time Savings”; Agilent Technologies; Copyright 2003; Copublished by the IEEE CS and the IEEE CASS; IEEE Design and Test of Computers; pp. 84-89.
Bill Eklow (Cisco Systems), Carl Barnhart (Cadence), Kenneth P. Parker (Agilent Technologies); “IEEE 1149.6: A Boundary-Scan Standard for Advanced Digital Networks”; Copyright 2003; Copublished by the IEEE CS and the IEEE CASS; IEEE Design and Test of Computers; pp. 76-83.
Darren Anand et al.; “An On-Chip Self-Repair Calculation and Fusing Methodology”; Copyright 2003; Copublished by the IEEE CS and the IEEE CASS; IEEE Design and Test of Computers; pp. 67-75.
Jansuz Rajski et al.; “Embedded Deterministic Test for Low-Cost Manufacturing”; Copyright 2003; Copublished by the IEEE CS and the IEEE CASS; IEEE Design and Test of Computers; pp. 58-66.
Robert Madge et al.; “Obtaining High Defect Coverage for Frequency-Dependent Defects in Complex ASICs”; Copyright 2003; Copublished by the IEEE CS and the IEEE CASS; IEEE Design and Test of Computers; pp. 46-53.
Bruce D. Cory et al.; “Speed Binning with Path Delay Test in 150-nm Technology”; Copyright 2003; Copublished by the IEEE CS and the IEEE CASS; IEEE Design and Test of Computers; pp. 41-45.
Alfred L. Crouch et al.; “AC Scan Path Selection for Physical Debugging”; Copyright 2003; Copublished by the IEEE CS and the IEEE CASS; IEEE Design and Test of Computers; pp. 34-40.
Stephen Pateras; “Achieving At-Speed Structural Test”; Copyright 2003; Copublished by the IEEE CS and the IEEE CASS; IEEE Design and Test of Computers; pp. 26-33.
Xijiang Lin et al.; “High-Frequency, At-Speed Scan Testing”; Copyright 2003; Copublished by the IEEE CS and the IEEE CASS; IEEE Design and Test of Computers; pp. 17-25.
Kee Sup Kim et al.; “Delay Defect Characteristics and Testing Strategies”; Copyright 2003; Copublished by the IEEE CS and the IEEE CASS; IEEE Design and Test of Computers; pp. 8-16.
Kenneth M. Butler et al.; “Guest Editors' Introduction: Speed Test and Speed Binning for Complex ICs”; Copyright 2003; Copublished by the IEEE CS and the IEEE CASS; IEEE Design and Test of Computers; pp. 6-7.
Xilinx, Inc.; “Virtex-II Pro X Platform FPGAs: Complete Data Sheet”; DS110 (v1.1); Advance Product Specification; Mar. 5, 2004; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California, 95124; pp. 185.
Xilinx, Inc.; “PowerPC Processor Reference Guide, Embedded Development Kit”; EDK 6.1 Sep. 2, 2003; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California, 95124; pp. 1-570.
Xilinx, Inc.; “PowerPC 405 Processor Block Reference Guide, Embedded Development Kit”; EDK 6.1 Oct. 6, 2003; available from Xilinx, Inc.; 2100 Logic Drive, San Jose, California, 95124; pp. 1-176.
Xilinx, Inc.; U.S. Appl. No. 10/836,995, filed Apr. 30, 2004 by Ansari et al.
Ansari Ahmad R.
Correale, Jr. Anthony
DeBruyne Leslie M.
Douglass Stephen M.
Herron Nigel G.
International Business Machines
Rossoshek Helen
Siek Vuthe
Webostad W. Eric
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