Speeding up timing analysis by reusing delays computed for...

Details Speeding up timing analysis by reusing delays computed for... Speeding up timing analysis by reusing delays computed for...

2005-08-04

2008-11-11

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C703S014000

Reexamination Certificate

active

07451412

ABSTRACT:
One embodiment of the present invention provides a system that speeds up timing analysis by reusing delays computed for isomorphic subcircuit. During operation, the system receives a circuit block to be analyzed, wherein the circuit block is in the form of a netlist. The system then subdivides the circuit block into a set of subcircuits. The subcircuits are then partitioned into equivalence classes, which contain subcircuits which are topologically isomorphic to each other. Next, the system performs a timing analysis by tracing paths through a timing graph for the circuit block. During this timing analysis, whenever a delay is required for a subcircuit, the system determines if a corresponding delay has been already computed for the equivalence class associated with the subcircuit. If so, the system reuses the delay. If not, the system computes the delay for the subcircuit, and then associates the computed delay with the equivalence class so that the computed delay can be reused for isomorphic subcircuits.

REFERENCES:
patent: 5831869 (1998-11-01), Ellis et al.
patent: 5966521 (1999-10-01), Takeuchi et al.
patent: 6009252 (1999-12-01), Lipton
patent: 6202192 (2001-03-01), Donath et al.
patent: 6286128 (2001-09-01), Pileggi et al.
patent: 6334205 (2001-12-01), Iyer et al.
patent: 6473881 (2002-10-01), Lehner et al.
patent: 6499129 (2002-12-01), Srinivasan et al.
patent: 6557145 (2003-04-01), Boyle et al.
patent: 6591402 (2003-07-01), Chandra et al.
patent: 6782511 (2004-08-01), Frank et al.
patent: 7143021 (2006-11-01), McGaughy et al.
patent: 7257525 (2007-08-01), McGaughy

Affiliated with

Also associated with

Rating

Speeding up timing analysis by reusing delays computed for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Speeding up timing analysis by reusing delays computed for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Speeding up timing analysis by reusing delays computed for... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4045649