Split I/O circuit for performance optimization of digital...

Details Split I/O circuit for performance optimization of digital... Split I/O circuit for performance optimization of digital...

1999-03-02

2001-07-31

Phan, Trong (Department: 2818)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06269468

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to digital circuit design technology, and particularly to circuits and methods for reducing power in and optimizing performance of digital/logic circuits.
BACKGROUND OF THE INVENTION
In current digital circuit designs, for example, in ASIC and programmable gate array designs, power and timing optimization is done on a per path basis. Standard techniques involve 1) changing the circuit power level, i.e., implementing higher (faster) or lower power versions of the same book (logic gate(s)) to meet the timing requirement of a critical path; 2) repower, either serially with a repowering tree, or in parallel by cloning or duplicating a path to speed up the critical nets. As a consequence of these methods, unnecessary loading of noncritical nets occur resulting in wasted AC power. In addition, increased wire congestion can occur as the number of books that the input nets have to fan out to doubles/triples to meet the performance paths.
With more particularity,
FIG. 1
a
shows a logic network
10
having a timing critical path starting at primary input pin C of NAND gate
1
going to input pin A of NAND gate
2
, and on to the critical output
15
of NAND gate
2
. Assume that all other paths
16
-
20
are non-timing critical. Thus,
FIG. 1
a
illustrates the very common occurrence of critical timing paths crossing non-critical timing paths on a logic network. There are three ways to correct the timing problems in this network: 1) increase NAND
1
to the highest power level required to correct the problem. If this can correct the timing problem, it will, at the very least, increase the power of the non-critical path through input pin A of NAND
1
; 2) if increasing the power level of the circuit does not solve the timing problem then: a) either serial repowering comprising the addition of a serial buffer
21
to the book of
FIG. 1
a
, as shown in
FIG. 1
b
; or, b) parallel repowering comprising the addition of logic NAND gate
23
duplicate of logic NAND gate
1
and connected in parallel with the original NAND gate
1
, as shown in
FIG. 1
c.
In both cases, power consumption, as well as wiring congestion, is increased by adding books. Thus, those non-critical paths
16
-
20
that cross critical paths are not power-optimized. This is because in order to obtain an optimal performance/power solution, the non-critical capacitance must be eliminated from the critical path to speed it up without increasing overall capacitance. FIG.
1
(
b
) only provides partial isolation of the critical capacitance C
crit
from the non-critical capacitance C
non-crit
since gate
1
still sees the load of the buffer. FIG.
1
(
c
) doubles the input capacitance of both the critical and non-critical paths, as well as increasing the area and wiring congestion.
Prior art techniques for optimizing (critical path) performance in such circuit designs may be found and described in U.S. Pat. No. 4,827,428 which describes a transistor sizing system for improving the design of integrated circuits; U.S. Pat. No. 4,940,908 which describes a technique for reducing critical speed path delays in binary logic circuits by implementing “multiplexing logic”, U.S. Pat. No. 5,815,004 which teaches a FPGA having independently buffered output lines of a configurable logic block for handling critical path situations; U.S. Pat. No. 5,517,132 which teaches a logic synthesis method utilizing two voltages, a higher voltage for driving critical paths and lower level voltages for driving non-critical paths, in an effort to reduce power consumption of integrated circuits; and, U.S. Pat. No. 5,787,011 which teaches a technique implementing complementary passage logic (CPL) technology using low power circuits for non-critical circuits and higher power circuits for critical paths. While effective for their respective purposes, it still remains the case that non-critical paths that cross critical paths cannot be power-optimized.
As shown in
FIG. 2
, the basic problem with traditional libraries is that a traditional book
25
comprising a logic stage
27
for receiving input signals and implementing logic, and a single output buffer stage
29
having a single output for driving fanout circuits is designed for a given power level. Moreover, these book designs assume that both inputs are equally critical and all output sinks are also critical paths. As shown in FIG.
1
(
a
), however, this is simply not the case.
What is required is a book design technique that can simultaneously support a critical high-performance/high-power path, and a non-critical low-power path, thus allowing simultaneous optimization of both power and performance.
SUMMARY OF THE INVENTION
The present invention is directed to a “split-book” logic circuit design having different active device sizes with outputs for connections to both critical and non-critical digital circuit paths. By using the “split” books designs with separate input and output stages, better silicon utilization, power optimization, and performance results. This is because each split book is designed with multiple output buffers that may be configured to optimally drive critical and non-critical paths. During the power/performance optimization phase of the design, timing critical paths of the design are first identified, with each path being optimized on its own basis. First the input stage of the timing critical path may be improved with a stronger drive on the input port of the book. Only the input port that has been linked to a critical path is updated. The other input pins are left at their default setting. Then, the output buffers may then be connected together according to criticality of the path and net capacitive load they are driving. Different split book input/output circuit combinations may be attempted during the design phase until an optimal tradeoff between power optimization and performance is reached.
According to the principles of the invention, there is provided: 1) a method of optimizing a design of a circuit, the method comprising the steps of identifying a circuit element that drives both a critical circuit path and a non-critical circuit path, which critical path fails a timing requirement of the circuit, and replacing the circuit element with a split I/O circuit; and 2) a split I/O circuit comprising a logic stage for receiving input signals and performing a logic evaluation in response to the input signals, an output stage coupled to the logic stage and to a plurality of outputs for driving a results of the logic evaluation therethrough, the outputs coupled to circuit paths having varying levels of criticality and load magnitudes, and wherein the output stage includes a plurality of driving circuits selectively coupled together to simultaneously drive an individual output based on a criticality level of a circuit path coupled to the individual output and on a load magnitude of the individual output.
The various features of novelty which characterize the invention are pointed out with particularity in the claims annexed to and forming a part of the disclosure. For a better understanding of the invention, its operating advantages, and specific objects attained by its use, reference should be had to the drawings and descriptive matter in which there are illustrated and described preferred embodiments of the invention.


REFERENCES:
patent: 4827428 (1989-05-01), Dunlop et al.
patent: 4940908 (1990-07-01), Tran
patent: 5003487 (1991-03-01), Drumm et al.
patent: 5319646 (1994-06-01), Simpson et al.
patent: 5347520 (1994-09-01), Simpson et al.
patent: 5517132 (1996-05-01), Ohara
patent: 5787011 (1998-07-01), Ko
patent: 5799170 (1998-08-01), Drumm et al.
patent: 5815004 (1998-09-01), Trimberger et al.
patent: 5903466 (1999-05-01), Beausang et al.
patent: 5984510 (1999-11-01), Guruswamy et al.

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