System and method for I/O synthesis and for assigning I/O to...
System and method for reducing the generation of...
System and method for statistical timing analysis of digital...
System and method of automated wire and via layout...
System and method of determining minimum cost path
System and method of providing a memory hierarchy
Techniques for generating microcontroller configuration...
Techniques for parallel buffer insertion
Test method and system for characterizing and/or refining an...
Three dimensional memory in a system on a chip
Timing analysis using statistical on-chip variation
Timing driven logic block configuration
Timing verification method and apparatus
Tool and method for automatically identifying minimum timing...
Top level hierarchy wiring via 1×N compiler
Transistor layout structures for controlling sizes of...
Tunneling as a boundary congestion relief mechanism
Use of smith chart to compensate for missing data on network...
Using selectable in-line inverters to reduce the number of...
Validating continuous signal phase matching in high-speed...