Timing analysis using statistical on-chip variation

Details Timing analysis using statistical on-chip variation Timing analysis using statistical on-chip variation

2011-08-02

2011-08-02

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S106000

Reexamination Certificate

active

07992114

ABSTRACT:
A statistical on-chip variation approach to timing analysis permits the automated or semi-automated selection of design-specific margins without requiring complex statistical libraries. By separately addressing the impact of random and systematic variations on timing, a design-specific margin can be obtained and used in downstream OCV analysis. In addition, where statistical libraries are available for some portions of a design, these can be incrementally included in the timing analysis to obtain more accurate results.

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