Timing driven logic block configuration

Details Timing driven logic block configuration Timing driven logic block configuration

2011-04-12

2011-04-12

Levin, Naum (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S108000, C716S113000

Reexamination Certificate

active

07926016

ABSTRACT:
A method of configuring a logic block of a programmable logic device (PLD) during physical implementation of a circuit design, wherein ports of the logic block are selectively registered, can include identifying the logic block of the PLD, wherein the logic block is located on a critical path. For each of a plurality of selectively registerable portions of the logic block, the method can include computing input slacks and output slacks based upon potential register usage within the logic block. The method further can include determining register usage for the logic block by maximizing a function which depends upon a measure of worst case slack for pipeline stages.

REFERENCES:
patent: 4873630 (1989-10-01), Rusterholz et al.
patent: 6086631 (2000-07-01), Chaudhary et al.
patent: 6487648 (2002-11-01), Hassoun
patent: 6581187 (2003-06-01), Gupta et al.
patent: 6711729 (2004-03-01), McElvain et al.
patent: 6957412 (2005-10-01), Betz et al.
patent: 7107568 (2006-09-01), Cronquist
patent: 7117277 (2006-10-01), Mathewson et al.
patent: 7157934 (2007-01-01), Teifel et al.
patent: 7203919 (2007-04-01), Suaris et al.
patent: 7234044 (2007-06-01), Perry
patent: 7360190 (2008-04-01), Singh et al.
patent: 7478356 (2009-01-01), Sundararajan et al.
patent: 7594208 (2009-09-01), Borer et al.
patent: 7607118 (2009-10-01), Hutton
patent: 2005/0132316 (2005-06-01), Suaris et al.
patent: 2006/0101369 (2006-05-01), Wang et al.
U.S. Appl. No. 11/241,314, filed Sep. 30, 2005, Sundararajan et al., Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
Xilinx, Inc.; “ExtremeDSP Design Considerations User Guide”; UG073 (v1.2), Feb. 4, 2005; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 1-54.

Affiliated with

Also associated with

Rating

Timing driven logic block configuration does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Timing driven logic block configuration, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Timing driven logic block configuration will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2668063