Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2011-04-19
2011-04-19
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S132000
Reexamination Certificate
active
07930667
ABSTRACT:
A system and method to optimize a circuit layout, and more particularly, to a system and method of post layout data preparation to optimize a circuit layout and reduce random and systematic wire and via opens and shorts. The method includes stripping existing vias in a design layout and determining design parameters of the design layout including wiring placement and dimensions. The method further includes optimizing via layout by placing vias away from edges of the wiring and adjacent vias.
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Bergman Reuter Bette L.
Landis Howard S.
Stamper Anthony K.
Sucharitaves Jeanne-Tania
Bowers Brandon W
Chiang Jack
International Business Machines - Corporation
Kotulak Richard
Roberts Mlotkowski Safran & Cole P.C.
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