Transistor layout structures for controlling sizes of...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing

Reexamination Certificate

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Details

C716S118000, C716S119000, C716S124000

Reexamination Certificate

active

07900176

ABSTRACT:
A structure for controlling the size of a transistor may include: an active region; a first gate line on the active region; one or more second gate lines on the active region; and source or drain regions arranged in three or more divided active regions that result from the first gate line and the one or more second gate lines dividing the active region into the divided active regions. A method of controlling the size of a transistor may include: arranging an active region; arranging a first gate line on the active region; arranging one or more second gate lines on the active region; arranging source or drain regions in three or more divided active regions; and controlling the size of the transistor by connecting to each other or separating from each other the source or drain regions using upper wires.

REFERENCES:
patent: 7052962 (2006-05-01), Lovejoy
patent: 2003/0173588 (2003-09-01), Bianchi
patent: 2005/0001216 (2005-01-01), Adkisson et al.
patent: 2006/0138465 (2006-06-01), Choi et al.
patent: 07-115178 (1995-05-01), None
patent: 2004-311824 (2004-11-01), None
patent: 2005-236210 (2005-09-01), None
patent: 10-1998-0013909 (1998-05-01), None
patent: 10-2001-0084292 (2001-09-01), None
patent: 10-2005-0002080 (2005-01-01), None
patent: 10-2005-0060179 (2005-06-01), None

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