Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2007-12-31
2011-11-01
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S113000, C716S134000, C716S136000, C716S139000
Reexamination Certificate
active
08051398
ABSTRACT:
Systems and methods are provided for refining a design cycle for an integrated circuit. An integrated circuit design is generated. A plurality of non-critical paths within the integrated circuit design are identified. A set of at least one of the plurality of non-critical paths is modified to produce a modified design in which the sensitivity of each of the set of non-critical paths to at least one parameter is enhanced. Each parameter is either a design parameter or a process parameter. An integrated circuit is fabricated according to the modified design. The fabricated integrated circuit is evaluated to measure a set of timing data representing each of the plurality of non-critical paths. The value of the parameter is determined from the measured set of timing data.
REFERENCES:
patent: 7590968 (2009-09-01), Becker et al.
patent: 2005/0050497 (2005-03-01), Tetelbaum
patent: 2006/0288322 (2006-12-01), Zhang et al.
patent: 2007/0288219 (2007-12-01), Zafar et al.
Bittlestone Clive D.
Butler Kenneth M.
Butler Stephanie Watts
Mason Mark E.
Brady W. James
Pessetto John R.
Siek Vuthe
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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