Timing verification method and apparatus

Details Timing verification method and apparatus Timing verification method and apparatus

2011-07-19

2011-07-19

Garbowski, Leigh Marie (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S108000, C716S113000

Reexamination Certificate

active

07984406

ABSTRACT:
A computer-implemented timing verification method for obtaining delay time for a signal propagated through a signal path and performing timing verification. The method stores a table including a wiring resistance variation amount and a wiring capacitance variation amount that are in accordance with a geometry deviation of a wire from a reference geometry, extracts a wiring structure of the signal path from a storage unit, extracts a wiring resistance variation amount and a wiring capacitance variation amount that correspond to the extracted wiring structure from the table, generates an on-chip-variation coefficient from the extracted wiring resistance variation amount and wiring capacitance variation amount, and calculates delay time for the signal propagated through the signal path based on the generated on-chip-variation coefficient.

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Japanese Office Action, Partial English-language translation, mailed May 10, 2011 for Japanese Application No. 2007-010361.

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