4F 2 EEPROM NROM memory arrays with vertical devices
4F-square memory cell having vertical floating-gate transistors
6¼ f2 DRAM cell structure with four nodes per...
60 degree bump placement layout for an integrated circuit...
6F2 Trench EDRAM cell with double-gated vertical MOSFET and...
8 bit per cell non-volatile semiconductor memory structure...
90 degree bump placement layout for an integrated circuit...
A P channel MIS type semiconductor device
A semiconductor device for extracting a signal used to monitor p
A-C:H ISFET device, manufacturing method, and testing...
A.c. switch triggered at a predetermined half-period
A.sub.4 MeSb.sub.3 O.sub.12 substrates and dielectric/buffer lay
A1 x In y Ga 1-x-y N mixture crystal substrate, method of...
A1GaInP light emitting diode
A1InGaP LED having reduced temperature dependence
Abatement of electron beam charging distortion during dimensiona
Abberation mark and method for estimating overlay error and...
Ablative etch resistant coating for laser personalization of int
Above via metal-to-metal antifuse
Above via metal-to-metal antifuses incorporating a tungsten via