Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Patent
1997-12-15
1999-10-05
Jackson, Jr., Jerome
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
257369, 257775, 324751, 324769, H01L 2358, H01L 2348
Patent
active
059628677
ABSTRACT:
The inspection and measurement of critical dimensions of patterned features during the manufacture of sub-micron integrated circuits relies heavily upon the scanning-electron-microscope(SEM). This instrument is capable of quick, clean, and accurate measurements of features on large in-process silicon wafers. However, such features are frequently isolated from the electrical ground of the microscope by virtue of their circuit design. This creates a charge build up from the electron beam in the SEM and causes distorted and indistinct images, incapable of being measured. Also, such static charge build-up can be destructive to certain circuit elements. This invention teaches the use of independent inspection test structures, fabricated in wafer saw kerf regions or within designated test sites, especially designed to provide a reduction or elimination of charge build up during SEM observation. The structures are built to follow conventional processing and carry the desired features to be examined at each successive process level. They are particularly useful for examining and measuring contact and via openings, and measuring interconnection metal line widths and spacings, including polysilicon structures.
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Ackerman Stephen B.
Jackson, Jr. Jerome
Saile George O.
Taiwan Semiconductor Manufacturing Company , Ltd.
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