Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2001-11-29
2002-12-17
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S780000
Reexamination Certificate
active
06495926
ABSTRACT:
BACKGROUND OF INVENTION
A typical computer system includes at least a microprocessor and some form of memory. The microprocessor has, among other components, arithmetic, logic, and control circuitry that interpret and execute instructions necessary for the operation and use of the computer system.
FIG. 1
shows a typical computer circuit board (
10
) having a microprocessor (
12
), memory (
14
), integrated circuits (
16
) that have various functionalities, and communication paths (
18
), i.e., buses and wires, that are necessary for the transfer of data among the aforementioned components on the circuit board (
10
).
Integrated circuits (
16
) and microprocessors (
12
), such as the ones shown in
FIG. 1
, are electrically connected, i.e., “mounted,” to the circuit board (
10
) via chip packages. A chip package houses semiconductor devices in strong, thermally stable, hermetically-sealed environments that provide a semiconductor device, e.g., an integrated circuit, with electronic connectivity to circuitry external to the semiconductor device.
FIG. 2
shows a typical chip package assembly. In
FIG. 2
, an integrated circuit (
20
) is mounted onto a chip package (
22
), where an active side (
24
) of the integrated circuit (
20
) is electrically interfaced to the chip package (
22
). Specifically, the integrated circuit (
20
) has bumps (
26
) on bond pads (also known in the art as “landing pads”) (not shown) formed on the active side (
24
) of the integrated circuit (
20
), where the bumps (
26
) are used as electrical and mechanical connectors. The integrated circuit (
20
) is inverted and bonded to the chip package(
22
) by means of the bumps (
26
). Various materials, such as conductive polymers and metals (referred to as “solder bumps”), are commonly used to form the bumps (
26
) on the integrated circuit (
20
).
As discussed above with reference to
FIG. 2
, the bumps (
26
) on the integrated circuit (
20
) serve as electrical pathways between components within the integrated circuit (
20
) and the chip package (
22
). Within the integrated circuit (
20
) itself, an arrangement of conductive pathways and metal layers form a means by which components in the integrated circuit (
20
) operatively connect to the bumps (
26
) located on an exterior region of the integrated circuit (
20
). To this end,
FIG. 3
a
shows a side view of the integrated circuit (
20
). The integrated circuit (
20
) has several metal layers, M
1
-M
8
, surrounded by some dielectric material (
28
), e.g., silicon dioxide. The metal layers, M
1
-M
8
, are connected to each other by conductive pathways (
30
) known as “vias.” Vias (
30
) are essentially holes within the dielectric material (
28
) that have been doped with metal ions. Further, those skilled in the art will understand that although
FIG. 2
shows only eight metal layers and a particular amount of vias, integrated circuits may have any number of metal layers and/or vias.
Circuitry (not shown) embedded on a substrate of the integrated circuit (
20
) transmit and receive signals and power via the metal layers, M
1
-M
8
, and the vias (
30
). Signals that need to be transmitted/received to/from components external to the integrated circuit (
20
) are propagated through the metal layers, M
1
-M
8
, and vias (
30
) to the top metal layer, M
8
. The top metal layer (also referred to and known as “power grid”), M
8
, then transmits/receives signals and power to/from the bumps (
26
) located on the active side (
24
) of the integrated circuit (
20
). With respect to the power and energy needed by the integrated circuit (
20
), power is delivered to the integrated circuit (
20
) from external sources through the bumps (
26
) and metal layers, M
1
-M
8
. The top metal layer, M
8
, on the integrated circuit (
20
) acts as an interface between the integrated circuit (
20
) and the external sources/signals of power.
FIG. 3
b
shows a top view of the integrated circuit (
20
) shown in
FIG. 3
a
. The top metal layer, M
8
, as shown in
FIG. 3
b
, has a number of parallel regions, otherwise known as “metal bars.” These metal bars alternate between bars connected to VDD and regions connected to Vss. Such a configuration helps reduce electromagnetic interference. The top metal layer, M
8
, is configured such that it is orthogonal with the metal layer below, M
7
, as shown in
FIG. 3
b
. Further, bumps (
26
) on the top metal layer, M
8
, are arranged in a non-uniform fashion with some areas of the top metal layer, M
8
, having larger numbers of bumps (
26
) than other areas.
SUMMARY OF INVENTION
According to one aspect of the present invention, an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises a first bump disposed on the first metal bar, a second bump disposed on the first metal bar, and a reference bump disposed on the second metal bar, where the first bump and the second bump are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 60 degrees.
According to another aspect, an integrated circuit having a top metal layer that has a first metal bar and a second metal bar comprises a first bump disposed on the first metal bar, a second bump disposed on the first metal bar, and a reference bump disposed on the second metal bar, where the first metal bar and the second metal bar are positioned such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 60 degrees.
A patterned bump array for a power grid of an integrated circuit comprises a reference bump disposed on a first metal bar, a first bump disposed on a second metal bar, and a second bump disposed on a second metal bar, where the first bump, the second bump, and the reference bump are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 60 degrees.
According to another aspect, a bump layout for a power grid of an integrated circuit comprises a reference bump disposed on a first metal bar, a first bump disposed on a second metal bar, and a second bump disposed on a second metal bar, where the first metal bar and the second metal bar are arranged such that an angle between a line from the reference bump to the first bump and a line from the reference bump to the second bump has a value substantially equal to 60 degrees.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.
REFERENCES:
patent: 5959346 (1999-09-01), Ochiai
patent: 6008532 (1999-12-01), Takamori
patent: 6037547 (2000-03-01), Blish, II
patent: 6088233 (2000-07-01), Iijima et al.
patent: 6097097 (2000-08-01), Hirose
patent: 6166441 (2000-12-01), Geryk
patent: 6554011 (2002-09-01), Hirano et al.
patent: 2001203261 (2001-07-01), None
Bobba Sudhakar
Liu Dean
Thorp Tyler
Clark Sheila V.
Rosenthal & Osha L.L.P.
Sun Microsystems Inc.
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