Charge-trapping memory arrays resistant to damage from...
CMOS device with asymmetric gate strain
Composite silicon nitride sidewall spacers for reduced...
FinFET with low gate capacitance and low extrinsic resistance
Hosting structure of nanometric elements and corresponding...
Memory devices with memory cell transistors having gate...
Method of spacer formation and source protection after self-alig
Nickel silicide process using UDOX to prevent silicide shorting
Scalable two transistor memory devices
Semiconductor component and method of manufacture
Semiconductor device and manufacturing method of the semiconduct
Semiconductor device and method for fabricating the same
Semiconductor device and method of manufacturing the same
Semiconductor device having a reduced leakage current and a...
Semiconductor device having increased gaps between gates
Semiconductor device having interconnection layer with...
Semiconductor device structure including multiple fets...
Spacer formation for precise salicide formation