Method of spacer formation and source protection after self-alig

Details Method of spacer formation and source protection after self-alig Method of spacer formation and source protection after self-alig

1999-06-18

2000-12-12

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Mosfet type gate sidewall insulating spacer

257346, H01L 27088

Patent

active

061603171

ABSTRACT:
The present invention provides a semiconductor device and a method for providing such a semiconductor device which allows a field oxide etch while minimizing the damage to the silicon. This method is particularly useful for smaller semiconductor devices, for example, such as a semiconductor device utilizing core source spacing less than 0.4 microns. A method according to the present invention for providing a semiconductor device comprises the steps of depositing a first spacer oxide layer over a core area and a peripheral area of a semiconductor device; etching the first spacer oxide layer at the source side of core cell area; depositing a second spacer oxide layer over the core area and the peripheral area, and etching the first and second spacer oxide layers over the peripheral area only.

REFERENCES:
patent: 5933730 (1999-08-01), Sun et al.

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