Scalable two transistor memory devices

Active solid-state devices (e.g. – transistors – solid-state diode – Mosfet type gate sidewall insulating spacer

Reexamination Certificate

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Details

C257S331000, C257S903000, C257S904000, C438S240000, C438S258000, C365S063000

Reexamination Certificate

active

07042107

ABSTRACT:
A memory device includes a semiconductor substrate, a first gate insulator on a first portion of a semiconductor substrate, a storage node on the first gate insulator, a tunnel junction barrier on the storage node and a data electrode on the layer tunnel junction barrier. The device further includes a second gate insulator layer on a sidewall of the tunnel junction barrier, a third gate insulator on a second portion of the substrate adjacent the tunnel junction barrier and a gate electrode on the second gate insulator and the third gate insulator. First and second impurity-doped regions are disposed in the substrate and are coupled by a channel through the first and second portions of the substrate. Fabrication of such a device is also describes.

REFERENCES:
patent: 5952692 (1999-09-01), Nakazato et al.
patent: 6475857 (2002-11-01), Kim et al.
patent: 6528896 (2003-03-01), Song et al.
patent: 6635921 (2003-10-01), Yi et al.
patent: 2002-96809 (2002-12-01), None
patent: 2003-29203 (2003-04-01), None
Ledford, Stephen, “Non-Volatile Memory Technology Overview,” Motorola Semiconductor Application Note, Doc. No. AN1837/D, Motorola, Inc., 2000, pp. 1-17.

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