FinFET with low gate capacitance and low extrinsic resistance

Details FinFET with low gate capacitance and low extrinsic resistance FinFET with low gate capacitance and low extrinsic resistance

2006-09-12

2006-09-12

Huynh, Andy (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Mosfet type gate sidewall insulating spacer

C257S213000, C438S135000, C438S142000

Reexamination Certificate

active

07105934

ABSTRACT:
A FinFET device and a method of lowering a gate capacitance and extrinsic resistance in a field effect transistor, wherein the method comprises forming an isolation layer comprising a BOX layer over a substrate, configuring source/drain regions above the isolation layer, forming a fin structure over the isolation layer, configuring a first gate electrode adjacent to the fin structure, disposing a gate insulator between the first gate electrode and the fin structure, positioning a second gate electrode transverse to the first gate electrode, and depositing a third gate electrode on the fin structure, the first gate electrode, and the second gate electrode, wherein the isolation layer is formed beneath the insulator, the first gate electrode, and the fin structure. The method further comprises sandwiching the second gate electrode with a dielectric material. The fin structure is formed by depositing an oxide layer over a silicon layer.

REFERENCES:
patent: 6118161 (2000-09-01), Chapman et al.
patent: 6635923 (2003-10-01), Hanafi et al.
patent: 6660596 (2003-12-01), Adkisson et al.
patent: 2003/0042531 (2003-03-01), Lee et al.
patent: 2003/0151077 (2003-08-01), Mathew et al.
patent: 2003/0178670 (2003-09-01), Fried et al.
patent: 2005/0098822 (2005-05-01), Mathew et al.
Lindert, et al., “Sub-60-nm Quasi-Planar FinFETs Fabricated Using a Simplified Process”, IEEE Electron Device Letters, vol. 22, No. 10, Oct. 2001, pp. 487-489.

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