Active solid-state devices (e.g. – transistors – solid-state diode – Mosfet type gate sidewall insulating spacer
Reexamination Certificate
2002-10-21
2004-10-19
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Mosfet type gate sidewall insulating spacer
C257S368000, C257S369000
Reexamination Certificate
active
06806584
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor device structures and, more particularly, to FET device structures formed on the same substrate, and to methods for fabrication.
BACKGROUND OF THE INVENTION
In CMOS technologies, NFET and PFET devices are optimized to achieve required CMOS performance. Very different dopant species are used for NFET and PFET devices, accordingly. These species have very different physical properties such as diffusion rate and maximum activated concentration. In conventional CMOS technologies, both NFET and PFET usually share the same spacer process and topology. In order to optimize CMOS performance, the spacers typically are of one maximum width and are designed to trade-off the performance between NFET and PFET. For example, if Arsenic and Boron are used as the source/drain dopants for NFET and PFET, respectively, it is known that a narrower spacer is better for NFET but a much wider one is better for PFET, because Arsenic diffuses much slower than Boron. In this case, the PFET is a limiting factor. Thus, the maximum width of all spacers is optimized for PFET, trading-off the NFET performance. See, for example: U.S. Pat. No. 5,547,894 (Mandelman et al., issued Aug. 20, 1996, entitled “CMOS Processing with Low High-Current FETS”); U.S. Pat. No. 4,729,006 (Dally et al., issued Mar. 1, 1988, entitled “Sidewall Spacers for CMOS Circuit Stress Relief/Isolation and Method for Making”); and U.S. Pat. No. 4,648,937 (Ogura et al., issued Mar. 10, 1987, entitled “Method of Preventing Asymmetric Etching of Lines in Sub-Micrometer Range Sidewall Images Transfer”); which are all incorporated by reference herein in their entireties.
It is a problem, therefore, to optimize spacer width and FET performance for both the NFET and the PFET on the same substrate.
OBJECTS OF THE INVENTION
The present invention solves this problem by using a dual-spacer width to permit optimizing NFET or PFET device performance independently on the same substrate.
It is a principal object of the present invention to optimize performances of two different MOS devices having a common semiconductor substrate.
It is an additional object of the present invention to optimize independently the performances of an NFET device and a PFET device formed on one substrate.
It is a further object of the present invention to increase the drive current performance of an NFET device while decreasing the short channel effect in a PFET.
SUMMARY OF THE INVENTION
According to the present invention, a semiconductor device structure includes at least two field effect transistors formed on a same substrate, the first field effect transistor including a spacer having a first width, the second field effect transistor including a spacer having a second width, the first width being different than the second width.
The present invention also includes a method (process) for fabricating the semiconductor device structure.
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Fung Ka Hing
Gilbert Percy V.
Abate Joseph P.
Prenty Mark V.
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