CMOS imager with storage capacitor

CMOS input buffer with NMOS gate coupled to V.sub.SS through und

CMOS integrated circuit

CMOS integrated circuit and method for implanting NMOS transisto

CMOS integrated circuit device with LDD n-channel transistor...

CMOS integrated circuit devices and substrates having buried...

CMOS integrated circuit devices and substrates having...

CMOS integrated circuit for lessening latch-up susceptibility

CMOS integrated circuit having PMOS and NMOS devices with differ

CMOS integrated circuit having PMOS and NMOS devices with...

CMOS integrated circuit with reduced susceptibility to PMOS punc

CMOS integrated circuitry with Halo and LDD regions

CMOS integrated circuits including source/drain plug

CMOS interface circuit formed in silicon-on-insulator substrate

CMOS inverter coupling circuit comprising vertical transistors

CMOS inverter using gate induced drain leakage current

CMOS inverters configured using multiple-gate transistors

CMOS latchup suppression by localized minority carrier lifetime

CMOS locos isolation for self-aligned NPN BJT in a BiCMOS proces

CMOS logic gate having buried channel NMOS transistor for semico