CMOS integrated circuitry with Halo and LDD regions

Details CMOS integrated circuitry with Halo and LDD regions CMOS integrated circuitry with Halo and LDD regions

1997-01-14

1998-05-05

Fahmy, Wael

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257371, 257376, H01L 2976, H01L 2994, H01L 31062

Patent

active

057478554

ABSTRACT:
A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; b) masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and c) in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration at a second depth within both the PMOS substrate area and the NMOS substrate area, the first energy level and the first depth being greater than the second energy level and the second depth, respectively. Methods of forming memory and other CMOS integrated circuitry are also disclosed involving optimization of different NMOS transistors.

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