CMOS integrated circuit and method for implanting NMOS transisto

Details CMOS integrated circuit and method for implanting NMOS transisto CMOS integrated circuit and method for implanting NMOS transisto

1996-12-06

1998-12-01

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, 257371, 257372, 257408, 257900, H01L 27088

Patent

active

058442766

ABSTRACT:
A transistor and a transistor fabrication method for forming an LDD structure in which the n-type dopants associated with an n-channel transistor are formed prior to the formation of the p-type dopants is presented. The n-type source/drain and LDD implants generally require higher activation energy (thermal anneal) than the p-type source/drain and LDD implants. The n-type arsenic source/drain implant, which has the lowest diffusivity and requires the highest temperature anneal, is performed first in the LDD process formation. Performing such a high temperature anneal first ensures minimum additional migration of subsequent, more mobile implants. Mobile implants associated with lighter and less dense implant species are prevalent in LDD areas near the channel perimeter. The likelihood of those implants moving into the channel is lessened by tailoring subsequent anneal steps to temperatures less than the source/drain anneal step.

REFERENCES:
patent: 4769686 (1988-09-01), Horiuchi et al.
patent: 5472887 (1995-12-01), Hutter et al.
patent: 5527722 (1996-06-01), Hutter et al.

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