CMOS integrated circuit devices and substrates having...

Details CMOS integrated circuit devices and substrates having... CMOS integrated circuit devices and substrates having...

2000-11-13

2003-10-14

Loke, Steven (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S616000, C257S348000, C257S350000

Reexamination Certificate

active

06633066

ABSTRACT:

RELATED APPLICATION
This application is related to Korean Application No. 00-00670, filed Jan. 7, 2000, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and fabrication methods, and more particularly, to MOS-based semiconductor devices and substrates and methods of forming same.
BACKGROUND OF THE INVENTION
Partially-depleted silicon-on-insulator (PDSOI) MOSFETs offer high speed and low power performance, but typically remain susceptible to parasitic floating body effects (FBE) which can seriously degrade device performance. Various techniques have been proposed for reducing FBE in SOI MOSFETs. One such technique includes using a narrow bandgap SiGe layer adjacent a source of an SOI NMOS field effect transistor. As will be understood by those skilled in the art, the use of a SiGe layer reduces the potential barrier for holes passing from the body region to the source region. Therefore, holes generated in the body region by impact ionization can more readily flow into the source region through the path of the p−Si(body)
+SiGe(source)
+Si(source). This and other related techniques are disclosed in articles by J. Sim et al. entitled “Elimination of Parasitic Bipolar-induced Breakdown Effects in Ultra-Thin SOI MOSFETs Using Narrow-Bandgap-Source (NBS) Structure,” IEEE Trans. Elec. Dev., Vol. 42, No. 8, pp. 1495-1502, August (1995) and M. Yoshimi et al. entitled “Suppression of the Floating-Body Effect in SOI MOSFETs by the Bandgap Engineering Method Using a Si
1−x
Ge
x
Source Structure,” IEEE Trans. Elec. Dev., Vol. 44, No. 3, pp. 423-429, March (1997). U.S. Pat. No. 5,698,869 to Yoshimi et al. entitled “Insulated-Gate Transistor Having Narrow-Bandgap-Source” also discloses the use of a narrow bandgap material within a source region of a MOSFET.
Techniques to reduce FBE and improve channel characteristics in MOSFETs are also described in U.S. Pat. No. 5,891,769 to Liaw et al. entitled “Method for Forming a Semiconductor Device Having a Heteroepitaxial Layer.” In particular, the '769 patent discloses the use of a strained channel region to enhance carrier mobility within MOSFETs. This strained channel region may be formed by growing a silicon layer on an as-grown relaxed or unstrained SiGe layer. U.S. Pat. No. 5,963,817 to Chu et al. entitled “Bulk and Strained Silicon on Insulator Using Selective Oxidation,” also discloses the use of SiGe layers, which selectively oxidize at faster rates relative to silicon, to improve FBE. Furthermore, U.S. Pat. Nos. 5,906,951 and 6,059,895 to Chu et al. disclose wafer bonding techniques and strained SiGe layers to provide SOI substrates. The use of wafer bonding techniques and SiGe layers to provide SOI substrates are also described in U.S. Pat. Nos. 5,218,213 and 5,240,876 to Gaul et al. Conventional techniques for forming SOI substrates are also illustrated by
FIGS. 1A-1D
and
2
A-
2
D. In particular,
FIG. 1A
illustrates the formation of a handling substrate having a porous silicon layer therein and an epitaxial silicon layer thereon and
FIG. 1B
illustrates the bonding of a supporting substrate to a surface of the epitaxial silicon layer. The supporting substrate may include an oxide layer thereon which is bonded directly to the epitaxial silicon layer using conventional techniques. As illustrated by
FIG. 1C
, a portion of the handling substrate is then removed to expose the porous silicon layer. This removal step may be performed by grinding or etching away a portion of the handling substrate or splitting the porous silicon layer. As illustrated by
FIG. 1D
, a conventional planarization technique may then be performed to remove the porous silicon layer and provide an SOI substrate having a polished silicon layer thereon and a buried oxide layer therein. The conventional technique illustrated by
FIGS. 1A-1D
is commonly referred to as an epi-layer transfer (ELTRAN) technique.
FIG. 2A
illustrates a step of forming a handling substrate having a silicon layer thereon by implanting hydrogen ions into a surface of the substrate to define a buried hydrogen implant layer therein. Then, as illustrated by
FIG. 2B
, a supporting substrate is bonded to the handling substrate. A portion of the handling substrate is then removed by splitting the bonded substrate along the hydrogen implant layer, as illustrated by
FIG. 2C. A
conventional planarization technique may then be performed to remove the hydrogen implant layer, as illustrated by FIG.
2
D. The conventional technique illustrated by
FIGS. 2A-2D
is commonly referred to as a “smart-cut” technique.
Unfortunately, although the use of strained silicon channel regions may enhance carrier mobility in both NMOS and PMOS devices, such strained regions typically degrade short channel device characteristics. Thus, notwithstanding the above-described techniques for forming MOSFETs and SOI substrates, there continues to be a need for improved methods of forming these structures that do not require the use of strained channel regions to obtain enhanced channel mobility characteristics, and structures formed thereby.
SUMMARY OF THE INVENTION
Embodiments of the present invention include semiconductor-on-insulator (SOI) substrates having buried Si
1−x
Ge
x
layers therein. A SOI substrate according to one embodiment of the present invention comprises a silicon wafer having an electrically insulating layer thereon and a Si
1−x
Ge
x
layer having a graded concentration of Ge therein extending on the electrically insulating layer. An unstrained silicon active layer is also provided in the SOI substrate. This unstrained silicon active layer extends on the Si
1−x
Ge
x
layer and forms a junction therewith. The unstrained silicon active layer also preferably extends to a surface of the SOI substrate, so that integrated circuit devices may be formed at the surface of the silicon active layer. To facilitate the use of relatively thin silicon active layers, the Si
1−x
Ge
x
layer is preferably epitaxially grown from the unstrained silicon active layer. This epitaxial growth step may include providing an unstrained silicon active layer (or initially epitaxially growing an unstrained silicon active layer on a substrate) and then continuing growth of a Si
1−x
Ge
x
layer on the active layer by increasing the concentration of Ge in a graded manner until a maximum desired Ge concentration is obtained. Further growth may then occur by reducing the concentration of Ge in a graded manner back to x=0. The grading of Ge in the Si
1−x
Ge
x
layer may constitute a linear grading.
The preferred SOI substrates may be fabricated by initially forming a handling substrate having an unstrained silicon layer therein and Si
1−x
Ge
x
layer extending on the silicon layer. A supporting substrate is then bonded to the handing substrate so that the Si
1−x
Ge
x
layer is disposed between the supporting substrate and the unstrained silicon layer. A portion of the handling substrate is then preferably removed from the supporting substrate to expose a surface of the silicon layer and define a semiconductor-on-insulator substrate having a buried Si
1−x
Ge
x
layer therein. Here, the buried Si
1−x
Ge
x
layer preferably has a graded concentration of Ge therein with a profile that decreases in a direction that extends from the supporting substrate to the surface of the silicon layer.
These methods may also include forming a handling substrate having an unstrained first silicon layer therein, a Si
1−x
Ge
x
layer extending on the first silicon layer and an unstrained or strained second silicon layer extending on the Si
1−x
Ge
x
layer. The bonding step may also be preceded by the step of thermally oxidizing the second silicon layer to define a thermal oxide layer on the Si
1−x
Ge
x
. The supporting substrate may also comprise an oxide surface layer thereon and the bonding step may comprise bonding the oxide surface layer to the therm

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