CMOS integrated circuit having PMOS and NMOS devices with...

Details CMOS integrated circuit having PMOS and NMOS devices with... CMOS integrated circuit having PMOS and NMOS devices with...

2000-05-09

2003-03-25

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S325000, C257S369000, C257S374000, C257S410000, C257S411000, C257S506000

Reexamination Certificate

active

06538278

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuits and more specifically to a CMOS integrated circuit wherein the PMOS and NMOS transistors have different dielectric properties.
2. Discussion of Related Art
Complimentary metal oxide semiconductor (CMOS) integrated circuits are widely used in logic applications such as in the design of very large scale integrated circuits such as microprocessor and microcontrollers.
As shown in
FIG. 1
, a CMOS integrated circuit
100
contains both n-type MOS (NMOS) transistors and p-type MOS (PMOS) transistors formed on a single substrate
106
. NMOS device
102
is formed on a p-type conductivity region
108
of substrate
106
and contains a gate electrode
110
formed on a gate dielectric gate layer
112
and a pair of n-type source/drain regions
114
formed on laterally opposite sides of gate electrode
110
. Similarly, PMOS device
104
is formed on a n-type conductivity region
116
of substrate
106
and contains the gate electrode
118
formed on gate dielectric layer
112
and a pair of p-type conductivity source/drain regions
120
formed along opposite sidewalls of gate electrode
118
.
In CMOS architecture for digital applications, such as microprocessors, NMOS and PMOS devices
102
and
104
, respectively, are operated in the “inversion mode” or they sit idle. To place PMOS transistor
104
in inversion mode, a negative gate voltage, V
gs
<V
t
, is applied to gate electrode
118
of PMOS transistor
104
to form an inversion channel
122
of p-type conductivity between source/drain regions
120
which allows current to flow from one source/drain region
120
to the other source/drain region
120
. To place NMOS device
102
in inversion mode, a positive gate voltage, V
gs
>V
t
is applied to gate electrode
110
of transistor
102
to form and inversion channel
124
of n-type conductivity between source/drain regions
114
to allow currents to travel from one. source/drain region
114
to the other source/drain region
114
.
Although CMOS integrated circuits are generally more difficult to manufacture because they contain both PMOS and NMOS devices on a single substrate, CMOS devices are necessary in order to reduce power consumption, especially in very large scale (VLSI) circuits such as microprocessors where literally millions of transistors are coupled together.
SUMMARY OF THE INVENTION
A CMOS integrated circuit having a PMOS and NMOS device with different gate dielectric layers is described. According to the present invention, an NMOS transistor is formed on a p-type conductivity region of a semiconductor substrate. The NMOS transistor has first gate dielectric layer formed on the p-type conductivity region. A PMOS transistor is formed on a n-type conductivity region of the semiconductor substrate. The PMOS transistor has a second gate dielectric layer wherein the second gate dielectric layer has a different composition than the first gate dielectric layer.


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