CMOS input buffer with NMOS gate coupled to V.sub.SS through und

Details CMOS input buffer with NMOS gate coupled to V.sub.SS through und CMOS input buffer with NMOS gate coupled to V.sub.SS through und

1994-07-14

1996-12-03

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257379, 257380, 257357, 257358, 257412, H01L 2978

Patent

active

055811051

ABSTRACT:
An input buffer for a CMOS integrated circuit comprises parallel pairs of complementary PMOS pull-up and NMOS pull-down transistors. For each NMOS transistor, a polysilicon NMOS gate lead structure includes three sections: a heavily doped gate section, an undoped resistor section, and a heavily doped contact section. The heavily doped contact section is contacted by a metal delivering a logic low voltage (V.sub.SS) so that the NMOS gate is resistively coupled to V.sub.SS. This resistance cooperates with the gate to drain resistance to define a voltage divider between V.sub.SS and V.sub.IN. This voltage divider leaves the gate at a small positive voltage during an electrostatic discharge event. This ensures that all NMOS transistors of a buffer become current bearing before any of them enters second breakdown. This arrangement maximizes input-buffer protection from electrostatic discharge events. The novel NMOS arrangement is readily compatible with CMOS fabrication techniques.

REFERENCES:
patent: 4760433 (1988-07-01), Young et al.
patent: 5140401 (1992-08-01), Ker et al.
patent: 5182621 (1993-01-01), Hinooka
patent: 5235201 (1993-08-01), Honna
patent: 5310694 (1994-05-01), Houston

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